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| ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 1 ? 2004?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. the powerpc name and logo are registered trademarks of ibm corp. and used under license. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their respective owners. virtex-4 fpga electrical characteristics virtex?-4 fpgas are available in -12, -11, and -10 speed grades, with -12 having the highest performance. virtex-4 fpga dc and ac characteristics are specified for both commercial and industrial grades. except the operat- ing temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -10 speed grade industrial device are the same as for a -10 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parame- ters included are common to popular designs and typical applications. this virtex-4 fpga data sheet is part of an overall set of documentation on the virtex-4 family of fpgas that is avail- able on the xilinx website: ? virtex-4 family overview, ds112 ? virtex-4 fpga user guide, ug070 ? virtex-4 fpga configuration guide, ug071 ? xtremedsp for virtex-4 fpgas user guide, ug073 ? virtex-4 fpga packaging and pinout specification, ug075 ? virtex-4 fpga pcb designer?s guide, ug072 ? virtex-4 rocketio? multi-gigabit transceiver user guide, ug076 ? virtex-4 fpga embedded tri-mode ethernet mac user guide, ug074 ? powerpc? 405 processor block reference guide, ug018 all specifications are subject to change without notice. virtex-4 fpga dc characteristics 0 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 00 product specification ta bl e 1 : absolute maximum ratings symbol description units v ccint internal supply voltage relative to gnd ?0.5 to 1.32 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.75 v v batt key memory battery backup supply ?0.5 to 4.05 v v ref input reference voltage ?0.3 to 3.75 v v in i/o input voltage relative to gnd (all user and dedicated i/os) ?0.75 to 4.05 v i/o input voltage relative to gnd (restricted to maximum of 100 user i/os) (3,4) ?0.95 to 4.4 (commercial temperature) ?0.85 to 4.3 (industrial temperature) v 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco + 0.5 v i in current applied to an i/o pin, powered or unpowered 100 ma total current applied to all i/o pins, powered or unpowered 200 ma
virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 2 v ts voltage applied to 3-state 3.3v output (all user and dedicated i/os) ?0.75 to 4.05 v voltage applied to 3-state 3.3v output (restricted to maximum of 100 user i/os) (3,4) ?0.95 to 4.4 (commercial temperature) ?0.85 to 4.3 (industrial temperature) v 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco + 0.5 v avccauxrx receive auxiliary supply voltage relative to analog ground, gnda (rocketio pins) ?0.5 to 1.32 v avccauxtx transmit auxiliary supply voltage relative to analog ground, gnda (rocketio pins) ?0.5 to 1.32 v avccauxmgt management auxiliary supply voltage relative to analog ground, gnda (rocketio pins) ?0.5 to 3.0 v v trx terminal receive supply voltage relative to gnd ?0.5 to 3.0 v v ttx terminal transmit supply voltage relative to gnd ?0.5 to 1.65 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (2) +220 c t j maximum junction temperature (2) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings mi ght cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at thes e or any other conditions beyond those li sted under operating conditions is not impli ed. exposure to absolute maximum ratings conditions for extended per iods of time might affect device reliability. 2. for soldering guidelines and thermal considerations, see the virtex-4 packaging and pinout specification on the xilinx website. 3. when using more than 100 3.3v i/os, refer to the virtex-4 fpga user guide , chapter 6, ?3.3v i/o design guidelines.? 4. for more flexibility in specific designs, a maximum of 100 user i/os can be stressed beyond the normal spec for no more than 20% of a data period. there are no bank restrictions. ta bl e 2 : recommended operating conditions symbol description min max units v ccint internal supply voltage relative to gnd, t j =0 c to +85 c commercial 1.14 1.26 v internal supply voltage relative to gnd, t j = ?40 c to +100 c industrial 1.14 1.26 v v ccaux auxiliary supply voltage relative to gnd, t j =0 c to +85 c commercial 2.375 2.625 v auxiliary supply voltage relative to gnd, t j = ?40 c to +100 c industrial 2.375 2.625 v v cco (1,3,4,5) supply voltage relative to gnd, t j =0 c to +85 c commercial 1.14 3.45 v supply voltage relative to gnd, t j = ?40 c to +100 c industrial 1.14 3.45 v v in 3.3v supply voltage relative to gnd, t j =0 c to +85 c commercial gnd ? 0.20 3.45 v 3.3v supply voltage relative to gnd, t j = ?40 c to +100 c industrial gnd ? 0.20 3.45 v 2.5v and below supply voltage relative to gnd, t j =0 c to +85 c commercial gnd ? 0.20 v cco +0.2 v 2.5v and below supply voltage relative to gnd, t j =?40 c to +100 c industrial gnd ? 0.20 v cco +0.2 v i in maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. commercial 10 ma industrial 10 ma v batt (2) battery voltage relative to gnd, t j =0 c to +85 ccommercial1.03.6v battery voltage relative to gnd, t j = ?40 c to +100 c industrial 1.0 3.6 v ta bl e 1 : absolute maximum ratings (continued) symbol description units virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 3 avccauxrx (6) auxiliary receive supply voltage relative to gnda commercial 1.14 1.26 v industrial 1.14 1.26 v avccauxtx (6) auxiliary transmit supply voltage relative to gnda commercial 1.14 1.26 v industrial 1.14 1.26 v avccauxmgt auxiliary management supply voltage relative to gnda commercial 2.375 2.625 v industrial 2.375 2.625 v v trx (7) terminal receive supply voltage relative to gnd commercial 0.25 2.5 v industrial 0.25 2.5 v v ttx terminal transmit supply voltage relative to gnd commercial 1.14 1.575 v industrial 1.14 1.575 v notes: 1. configuration data is retained even if v cco drops to 0v. 2. v batt is required only when usi ng bitstream encryption. if ba ttery is not used, connect v batt to either ground or v ccaux . 3. for 3.3v i/o operation, refer to the virtex-4 fpga user guide . 4. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v 5. the configuration output supply voltage v cc_config is also known as v cco_0 6. important! all unused rocketio transceivers must be connected to power and gnd. when using rocketio transceivers, refer to th e power filtering section of the virtex-4 rocketio multi-gigabi t transceiver user guide . unused transceivers must be powered by an appropriate voltage level source. passive filtering must meet t he requirements discussed in the virtex-4 rocketio multi-gigabit transceiver user guide . 7. internal ac coupling is enabled. ta bl e 2 : recommended operating conditions (continued) symbol description min max units ta bl e 3 : dc characteristics over re commended operating conditions symbol description data rate (gb/s) min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.9 v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 v i ref v ref current per pin 10 a i l input or output leakage current per pin (sample-tested) 10 a c in input capacitance (sample-tested) 10 pf i rpu (1) pad pull-up (when selected) @ v in =0v, v cco =3.3v 5 200 a pad pull-up (when selected) @ v in =0v, v cco =3.0v 5 125 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 5 120 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 5 60 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 5 40 a i rpd (1) pad pull-down (when selected) @ v in =v cco 5 100 a i batt (1) battery supply current 75 100 na i ccauxrx (2) operating avccauxrx supply current 6.5 292 427 ma 5.0 302 485 ma 4.25 291 446 ma 3.125 279 382 ma 1.25/2.5 263 351 ma 1.25 digital rx 314 432 ma virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 4 i ccauxtx (2) operating avccauxtx supply current 6.5 170 339 ma 5.0 180 355 ma 4.25 173 330 ma 3.125 165 307 ma 2.5 157 298 ma 1.25 151 295 ma i ccauxmgt (2) operating avccauxmgt supply current 3 5 ma i ttx (2) operating i ttx supply current when transmitter is ac coupled or v ttx =v trx 100 210 ma i trx (2,3) operating i trx supply current when receiver is ac coupled or v ttx =v trx 12 24 ma n temperature diode ideality factor 1.02 n p cpu power dissipation of powerpc 405 processor block 0.45 mw/mhz r series resistance 2 notes: 1. values are specified at nominal voltage, 25c. 2. typical i cc numbers given per tile with both mgts operating with default settings. maximum i cc numbers given per tile wi th both mgts operating with maximum amplitude and emphasis settings. 3. varies with ac / dc coupling. ta bl e 3 : dc characteristics over re commended operating conditions (continued) symbol description data rate (gb/s) min typ max units ta bl e 4 : quiescent supply current symbol description device typ (1) max units i ccintq quiescent v ccint supply current xc4vlx15 46 note (6) ma xc4vlx25 77 note (6) ma xc4vlx40 121 note (6) ma xc4vlx60 167 note (6) ma xc4vlx80 220 note (6) ma xc4vlx100 292 note (6) ma xc4vlx160 384 note (6) ma xc4vlx200 489 note (6) ma xc4vsx25 94 note (6) ma xc4vsx35 140 note (6) ma xc4vsx55 271 note (6) ma xc4vfx12 47 note (6) ma xc4vfx20 71 note (6) ma xc4vfx40 139 note (6) ma xc4vfx60 203 note (6) ma xc4vfx100 311 note (6) ma xc4vfx140 442 note (6) ma virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 5 i ccoq quiescent v cco supply current xc4vlx15 1.25 note (6) ma xc4vlx25 1.25 note (6) ma xc4vlx40 1.25 note (6) ma xc4vlx60 1.5 note (6) ma xc4vlx80 1.5 note (6) ma xc4vlx100 1.75 note (6) ma xc4vlx160 2.5 note (6) ma xc4vlx200 2.5 note (6) ma xc4vsx25 1.25 note (6) ma xc4vsx35 1.25 note (6) ma xc4vsx55 1.5 note (6) ma xc4vfx12 1.25 note (6) ma xc4vfx20 1.25 note (6) ma xc4vfx40 1.25 note (6) ma xc4vfx60 1.5 note (6) ma xc4vfx100 1.75 note (6) ma xc4vfx140 2.5 note (6) ma i ccauxq quiescent v ccaux supply current xc4vlx15 31 note (6) ma xc4vlx25 36 note (6) ma xc4vlx40 43 note (6) ma xc4vlx60 74 note (6) ma xc4vlx80 83 note (6) ma xc4vlx100 95 note (6) ma xc4vlx160 133 note (6) ma xc4vlx200 150 note (6) ma xc4vsx25 62 note (6) ma xc4vsx35 70 note (6) ma xc4vsx55 91 note (6) ma xc4vfx12 31 note (6) ma xc4vfx20 35 note (6) ma xc4vfx40 69 note (6) ma xc4vfx60 80 note (6) ma xc4vfx100 98 note (6) ma xc4vfx140 143 note (6) ma i ccauxrx (4) quiescent avccauxrx supply current xc4vfx20 25 154 ma xc4vfx60 35 154 ma xc4vfx100 50 154 ma ta bl e 4 : quiescent supply current (continued) symbol description device typ (1) max units virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 6 i ccauxtx (4) quiescent avccauxtx supply current xc4vfx20 10 44 ma xc4vfx60 15 44 ma xc4vfx100 20 44 ma i ttx (4,5) quiescent v ttx supply current xc4vfx20 1 2 ma xc4vfx60 1 2 ma xc4vfx100 1 2 ma i trx (4,5) quiescent v trx supply current xc4vfx20 1 2 ma xc4vfx60 1 2 ma xc4vfx100 1 2 ma i auxmgt (4) quiescent v auxmgt supply current xc4vfx20 1 2 ma xc4vfx60 1 2 ma xc4vfx100 1 2 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. typical values are for blank c onfigured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the power estima tor or xpower tool. 4. given for entire die. powered and unconfigured. 5. unconnected (if channel is driven to voltage). 6. use the xpower estimator (xpe) tool to calculate maximum stat ic power for specific process, voltage, and temperature conditio ns. ta bl e 4 : quiescent supply current (continued) symbol description device typ (1) max units virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 7 power-on power supply requirements xilinx? fpgas require a certai n amount of supply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. the power supplies can be turned on in any sequence, though the specifications shown in ta b l e 5 are for the rec- ommended power-on sequence of v ccint , v ccaux , v cco . xilinx does not specify the current for other power-on sequences. ta b l e 5 shows the minimum current required by virtex-4 devices for proper power-on and configuration. if the current minimums shown in ta bl e 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. once initialized and configured, use the xpower tool to esti- mate current drain on these supplies. ta bl e 5 : power-on current for virtex-4 devices device i ccintmin i ccauxmin i ccomin units typ (1) max (2) typ (1) max (2) typ (1) max (2) xc4vlx15 110 750 60 100 50 75 ma xc4vlx25 160 1350 85 125 75 100 ma xc4vlx40 250 1500 110 150 75 105 ma xc4vlx60 300 1925 225 300 150 250 ma xc4vlx80 400 2550 280 350 150 275 ma xc4vlx100 500 3200 335 425 200 300 ma xc4vlx160 700 3700 500 600 250 400 ma xc4vlx200 850 3850 500 600 250 400 ma xc4vsx25 175 725 110 150 75 105 ma xc4vsx35 250 1350 165 200 100 150 ma xc4vsx55 400 2225 225 300 150 225 ma xc4vfx12 111 750 56 100 50 75 ma xc4vfx20 151 1100 56 100 75 125 ma xc4vfx40 244 1650 167 250 125 225 ma xc4vfx60 339 2250 222 350 150 275 ma xc4vfx100 511 3300 278 500 200 300 ma xc4vfx140 702 4250 500 825 250 375 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum values are specified under worst-case process, voltage, and temperature conditions. ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage rela tive to gnd 0.20 to 50.0 ms virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 8 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recom- mended operating conditions at the v ol and v oh test points. only selected standards are tested. these are cho- sen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : selectio dc input and output levels iostandard attribute v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.2 0.8 2.0 3.45 0.4 2.4 note(3) note(3) lvcmos33, lvdci33 ?0.2 0.8 2.0 3.45 0.4 v cco ?0.4 note(3) note(3) lvcmos25, lvdci25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ?0.4 note(3) note(3) lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco +0.3 0.4 v cco ?0.45 note(4) note(4) lvcmos15, lvdci15 ?0.3 35% v cco 65% v cco v cco +0.3 0.4 v cco ?0.45 note(4) note(4) pci33_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 pci66_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 pci-x (5) ?0.2 35% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 gtlp ?0.3 v ref ?0.1 v ref + 0.1 ? 0.6 n/a 36 n/a gtl ?0.3 v ref ?0.05 v ref + 0.05 ? 0.4 n/a 32 n/a hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 24 ?8 hstl iv (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 48 ?8 diff hstl ii (2) ?0.3 50% v cco ?0.1 50% v cco +0.1 v cco +0.3 0.4 v cco ?0.4 ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 0.5 v cco ?0.5 ? ? sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 0.4 v cco ?0.4 ? ? notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. lvcmos using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. lvcmos using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. for more information on pci33_3, pci66_3, and pci-x, refer to the virtex-4 fpga user guide , selectio resources, chapter 6 . virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 9 ldt dc specifi cations (ldt_25) lvds dc specifications (lvds_25) ta bl e 8 : ldt dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential ou tput voltage (1,2) r t = 100 across q and q signals 495 600 715 mv v od change in v od magnitude ?15 15 mv v ocm output common mode voltage r t = 100 across q and q signals 495 600 715 mv v ocm change in v ocm magnitude ?15 15 mv v id input differential voltage 200 600 1000 mv v id change in v id magnitude ?15 15 mv v icm input common mode voltage 440 600 780 mv v icm change in v icm magnitude ?15 15 mv notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals 1.602 v v ol output low voltage for q and q r t = 100 across q and q signals 0.898 v v odiff differential ou tput voltage (1,2) (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 247 350 454 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.125 1.250 1.375 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 10 extended lvds dc specif ications (lvdsext_25) lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower com- mon-mode ranges. ta bl e 1 1 summarizes the dc output specifications of lvpecl. fo r more information on using lvpecl , see the virtex-4 fpga user guide : chapter 6, selectio resources . ta bl e 1 0 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.785 v v ol output low voltage for q and q r t = 100 across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 440 ? 820 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.125 1.250 1.375 v v idiff differential input voltage (1,2) (q ? q ), q = high (q ?q), q = high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differential input voltage = 350 mv 0.3 1.2 2.2 v notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 1 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 2.2 v v idiff differential input voltage (1,2) 0.100 1.5 v notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 11 rocketio dc input and output levels ta bl e 1 2 summarizes the dc input and output specifica- tions of the virtex-4 fpga rocketio multi-gigabit serial transceivers. figure 1 shows the single-ended output volt- age swing. figure 2 shows the peak-to-peak differential out- put voltage. consult the virtex-4 rocketio multi-gigabit transceiver user guide for further details. ta bl e 1 2 : rocketio dc specifications dc parameter symbol conditions min typ max units peak-to-peak differential input voltage dv in internal ac coupled 110 2400 mv single-ended input range se vin internal ac coupled 0 v trx mv common mode input voltage range v icm internal ac coupled 100 v trx ?100 mv bypassed internal ac coupled (1) 800 mv single-ended output voltage swing (2, 3) v out 450 725 mv common mode output voltage range (3) v tcm 1000 mv peak-to-peak differ ential output voltage (2, 3) dv ppout 900 1050 1400 mv signal detect threshold rxoob vdpp rx tbd electrical idle amplitude txoob vdpp tx 65 mv rocketio mgt clock dc input levels peak-to-peak differential input voltage v idiff 2 x | v mgtclkp ? v mgtckln | 100 600 2000 mv differential input resistance r in 71 105 124 notes: 1. the maximum v trx is 1.26v when bypassing the internal ac coupled v icm . v trx must be less than or equal to avccauxrx. 2. the output swing and pre-emphasis levels ar e selected using the attributes discussed in chapter 4: pma analog considerations in the virtex-4 rocketio multi-gigabit transceiver user guide for details. 3. v ttx is 1.5 5%; different amplitudes possible with adjusted dac values. figure 1: single-ended output voltage swing figure 2: peak-to-peak differential output voltage 0 +v txp txn dv out d s3 02_02_0 3 170 8 0 +v ?v txp?txn dv ppout d s3 02_0 3 _0 3 170 8 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 12 interface performan ce characteristics switching characteristics switching characteristics are specified on a per-speed- grade basis and can be designated as advance, prelimi- nary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. preliminary these specifications are based on complete es (engineer- ing sample) silicon characte rization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production sili- con. the probability of under-reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been char- acterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slow- est speed grades transition to production before faster speed grades. ta bl e 1 4 correlates the current status of each virtex-4 device with a corresponding speed specification version 1.68 designation. ta bl e 1 3 : interface performance description speed grade -12 -11 -10 networking applications sfi-4.1 (sdr lvds interface) (1) 710 mhz 710 mhz 645 mhz spi-4.2 (ddr lvds interface) 1 gb/s 1 gb/s 800 mb/s memory interfaces ddr2 sdram (high-performance serdes design) (2) 600 mb/s 533 mb/s 500 mb/s ddr2 sdram (low-latency direct clocking design) (3) 420 mb/s 410 mb/s 400 mb/s qdrii sram (low-latency direct clocking design) (4) 550 mb/s 500 mb/s 400 mb/s ddr sdram (low-latency direct clocking design) (5) 344 mb/s 336 mb/s 330 mb/s rldram ii (low-latency direct clocking design) (6) 470 mb/s 470 mb/s 400 mb/s notes: 1. input clocks above 622 mhz require ac coupling. 2. performance defined using design implem entation described in application note xapp721 , high-performance ddr2 sdram interface data capture using iserdes and oserdes . 3. performance defined using design implem entation described in application note xapp702 , ddr2 controller using virtex-4 devices . 4. performance defined using design implem entation described in application note xapp703 , qdr ii sram interface for virtex-4 devices . 5. performance defined using design implem entation described in application note xapp709 , ddr sdram controller using virtex-4 fpga devices . 6. performance defined using design implem entation described in application note xapp710 , synthesizable cio ddr rldram ii controller for virtex-4 fpgas . table 14: virtex-4 device speed grade designations device speed grade designations advance preliminary production xc4vlx15 -12, -11, -10 xc4vlx25 -12, -11, -10 xc4vlx40 -12, -11, -10 xc4vlx60 -12, -11, -10 xc4vlx80 -12, -11, -10 xc4vlx100 -12, -11, -10 xc4vlx160 -12, -11, -10 xc4vlx200 -11, -10 xc4vsx25 -12, -11, -10 xc4vsx35 -12, -11, -10 xc4vsx55 -12, -11, -10 xc4vfx12 -12, -11, -10 xc4vfx20 -12, -11, -10 xc4vfx40 -12, -11, -10 xc4vfx60 -12, -11, -10 xc4vfx100 -12, -11, -10 xc4vfx140 -11, -10 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 13 since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. all specifications are always representative of worst-case supply voltage and junction temperature conditions. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test pat- terns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development syst em) and back-ann otate to the simulation net list. unless ot herwise noted, values apply to all virtex-4 devices. powerpc switching characteristics consult the powerpc 405 processor block reference guide for further information. ta bl e 1 5 : powerpc 405 processor clocks absolute ac characteristics description speed grade units -12 -11 -10 minmaxminmaxminmax characteristics when apu not used cpmc405clock frequency (1,4) 045004000350mhz cpmdcrclk (3) 045004000350mhz cpmfcmclk (3) na na na na na na mhz jtagc405tck frequency (2) 022502000175mhz plbclk (3) 045004000350mhz bramdsocmclk (3) 045004000350mhz bramisocmclk (3) 045004000350mhz characteristics when apu used cpmc405clock frequency (1,4) 033302750233mhz cpmdcrclk (3) 033302750233mhz cpmfcmclk (3) 033302750233mhz jtagc405tck frequency (2) 0166.50137.50116.5mhz plbclk (3) 033302750233mhz bramdsocmclk (3) 033302750233mhz bramisocmclk (3) 033302750233mhz notes: 1. worst-case dcm output clock jitter is included in these specifications. 2. the theoretical maximum frequency of this clock is one-half the cpmc405clock. howeve r, the achievable maximum is system depen dent, and will be much less. 3. the theoretical maximum frequency of thes e clocks is equal to the cpmc405clock. int eger clock ratios are required for the cpm c405clock and bramdsocmclk, cpmc405clock and bramisocmclk, cpmc405clock and cpmdcrclk, cpmc405clock and cpmfcmclk, and cpmc405clock and plbclk. the integer ratios can be different for each interface. however, the achievable maximum is system depe ndent. 4. maximum operating frequency of cpmc405clock is specified wi th the input pin tiec405disoperandfwd connected to a logic 1. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 14 ta bl e 1 6 : processor block switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (cpmc405clock) clock and power management control inputs t ppcdck _corecki/ t ppcckd _corecki 0.60 0.20 0.65 0.20 0.74 0.23 ns, min reset control inputs t ppcdck _rstchip/ t ppcckd _rstchip 0.60 0.20 0.65 0.20 0.74 0.23 ns, min debug control inputs t ppcdck _exbushak/ t ppcckd _exbushak 0.60 0.20 0.65 0.20 0.74 0.23 ns, min trace control inputs t ppcdck _trcdis/ t ppcckd _trcdis 0.60 0.20 0.65 0.20 0.74 0.23 ns, min external interrupt controller control inputs t ppcdck _cinpirq/ t ppcckd _cinpirq 1.04 0.20 1.15 0.20 1.40 0.23 ns, min clock to out clock and power management control outputs t ppccko _coreslp 1.35 1.51 1.74 ns, max reset control outputs t ppccko _rstchip 1.441.591.83ns, max debug control outputs t ppccko _dbgldapu 1.34 1.48 1.70 ns, max trace control outputs t ppccko _trccycle 1.52 1.68 1.83 ns, max clock cpmc405clock minimum pulse width, high t cpwh 1.11 1.25 1.43 ns, min cpmc405clock minimum pulse width, low t cpwl 1.11 1.25 1.43 ns, min ta bl e 1 7 : processor block plb switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relati ve to clock (plbclk) processor local bus (icu/dcu) control inputs t ppcdck _icubusy/ t ppcckd _icubusy 0.60 0.20 0.66 0.20 0.76 0.23 ns, min processor local bus (icu/dcu) data inputs t ppcdck _icurddb/ t ppcckd _icurddb 0.90 0.20 1.00 0.20 1.15 0.23 ns, min clock to out processor local bus (icu /dcu) control outputs t ppccko _dcuabort 1.61 1.78 2.05 ns, max processor local bus (icu/d cu) address bus outputs t ppccko _icuabus 1.66 1.85 2.13 ns, max processor local bus (icu /dcu) data bus outputs t ppccko _dcuwrdbus 2.08 2.24 2.57 ns, max ta bl e 1 8 : processor block jtag switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (jtagc405tck) jtag control inputs t ppcdck _jtgtdi t ppcckd _jtgtdi 1.16 0.20 1.29 0.20 1.48 0.23 ns, min jtag reset input t ppcdck _jtgtrstn t ppcckd _jtgtrstn 0.60 0.20 0.65 0.20 0.74 0.23 ns, min clock to out jtag control outputs t ppccko _jtgtdo 1.68 1.79 2.14 ns, max virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 15 ta bl e 1 9 : powerpc 405 data-side on-chip memory switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (bramdsocmclk) data-side on-chip memo ry data bus inputs t ppcdck _dsocmrddb t ppcckd _dsocmrddb 0.60 0.20 0.65 0.20 0.74 0.23 ns, min clock to out data-side on-chip memory control outputs t ppccko _brambwr 2.07 2.30 2.65 ns, max data-side on-chip memory address bus outputs t ppccko _bramabus 2.07 2.30 2.65 ns, max data-side on-chip memory data bus outputs t ppccko _ibramwrdbus01 1.61 1.79 2.06 ns, max ta bl e 2 0 : powerpc 405 instruction-side on-chi p memory switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (bramisocmclk) instruction-side on-chip memory data bus inputs t ppcdck _isocmrddb t ppcckd _isocmrddb 0.74 0.20 0.82 0.20 0.94 0.23 ns, min clock to out instruction-side on-chip memory control outputs t ppccko _ibramen 3.04 3.37 3.88 ns, max instruction-side on-chip memory address bus outputs t ppccko _ibramrdabus 1.67 1.85 2.13 ns, max instruction-side on-chip memory data bus outputs t ppccko _ibramwrdbus 1.67 1.86 2.14 ns, max ta bl e 2 1 : processor block dcr bus switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (cpmdcrclock) device control register bus control inputs t ppcdck _exdcrack t ppcckd _exdcrack 0.12 0.15 0.13 0.17 0.15 0.19 ns, min device control register bus data inputs t ppcdck _exdcrdbusi t ppcckd _exdcrdbusi 0.57 0.16 0.57 0.16 1.02 0.27 ns, min clock to out device control register bus control outputs t ppccko _exdcrrd 1.20 1.35 1.54 ns, max device control register bus address bus outputs t ppccko _exdcrabus 1.28 1.45 1.66 ns, max device control register bus data bus outputs t ppccko _exdcrdbuso 1.31 1.45 1.67 ns, max virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 16 rocketio switching characteristics consult the virtex-4 rocketio multi-giga bit transceiver user guide for further information. ta bl e 2 2 : processor block apu interface switching characteristics description symbol speed grade units -12 -11 -10 setup and hold relative to clock (cpmdfcmclock) apu bus control inputs t ppcdck _dcdcren t ppcckd _dcdcren 0.33 0.20 0.36 0.20 0.42 0.23 ns, min apu bus data inputs t ppcdck _result t ppcckd _result 0.61 0.20 0.67 0.20 0.78 0.23 ns, min clock to out apu bus control outputs t ppccko _apufcmdec 1.53 1.75 2.00 ns, max apu bus data outputs t ppccko _radata 1.53 1.75 2.00 ns, max ta bl e 2 3 : maximum rocketio transceiver performance description speed grade units -12 -11 -10 rocketio transceiver 6.5 6.5 3.125 gb/s ta bl e 2 4 : rocketio reference clock switching characteristics description symbol conditions min typ max units reference clock frequency range (1) f gclk clk -10 speed grade 106 400 mhz -11/-12 speed grades 106 644 mhz all speed grades grefclk reference clock frequency range (1) f grefclk clk 106 320 mhz reference clock frequency tolerance f gtol clk ?350 +350 ppm reference clock rise time t rclk 20% ? 80% 400 ps reference clock fall time t fclk 20% ? 80% 400 ps reference clock duty cycle t dcref clk 45 55 % reference clock total jitter, peak-peak (2) t gjtt clk 40 ps clock recovery frequency acquisition time t lock initial lock of the pll from startup (programmable) 1ms spread spectrum clocking (3) 0% to ?0.5% 30 33 khz notes: 1. mgtclk input can be used for all serial bit rates. grefclk can be used for serial bit rates up to 1 gb/s. 2. measured at the package pin. for serial rates equal to or above 1 gb/s, mgtclk must be used. ui = unit interval. 3. tested with synchronous reference clock. figure 3: reference clock timing parameters d s3 02_04_0 3 170 8 8 0 % 20 % t fclk t rclk virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 17 ta bl e 2 5 : rocketio receiver switching characteristics description symbol conditions min typ max units serial data rate, -10 f grx 0.622 3.125 gb/s serial data rate, -11 f grx 0.622 6.5 gb/s xaui receive jitter tolerance (8b/10b cjpat) (2 ) rate (gb/s) mode (3 ) frequency receive deterministic jitter tolerance t djtol 3.125 acdr 0.37 ui (1) receive total jitter tolerance t tjtol (6) 3.125 acdr 0.65 receive sinusoidal jitter tolerance t sjtol (7) 3.125 acdr f = 22.1 khz 8.5 3.125 acdr f = 1.875 mhz 0.10 3.125 acdr f = 20 mhz 0.10 general receive jitter tolerance rate (gb/s) mode (3 ) pattern receive deterministic jitter tolerance t djtol (2,4) 6.5 (5) acdr prbs7 0.65 ui (1) 5.0 (5) acdr prbs7 0.65 4.25 (5) acdr prbs7 0.65 3.125 acdr prbs7 0.60 2.5 acdr prbs7 0.55 1.25 acdr prbs7 0.50 1.25 dcdr prbs7 0.50 1.25 dcdr prbs31 0.40 0.622 dcdr prbs31 0.40 sinusoidal jitter tolerance t sjtol 6.5 (9) acdr prbs7 0.65 5.0 (9) acdr prbs7 0.65 4.25 (9) acdr prbs7 0.65 3.125 (8) acdr prbs7 0.50 2.5 (8) acdr prbs7 0.50 1.25 (8) acdr prbs7 0.50 1.25 (8) dcdr prbs7 0.55 1.25 (8) dcdr prbs31 0.35 0.622 (8) dcdr prbs31 0.55 rxusrclk frequency t rx for slower speed grades = maxdatarate/32 250 mhz rxusrclk2 frequency t rx2 250 mhz rxusrclk duty cycle t rxdc 40 60 % rxusrclk2 duty cycle t rx2dc 40 60 % differential input skew t iskew 20 ps differential receive input sensitivity (2) v eye 110 mv on-chip ac coupling corner frequency signal detect response time rxsigdet responsetime 30 ns input capacitance at the die c die ff excess capacitance at the solder ball c ball ff notes: 1. ui = unit interval 2. using receiver equalization setting of 111 (14 db). 3. acdr = analog cdr and dcdr = digital cdr. 4. deterministic jitter (dj) is com posed of 75% isi + 25% high frequency sinusoidal jitter (sj). 5. deterministic jitter (dj) composed of isi + 0.10 ui of high frequency sj + 0.15 ui of rj. 6. sum of dj, random jitter (rj) of at least 0.55 ui, and sinusoidal jitter as defined by mask in ieee std 802.3ae-2002, figure 47-5 . 7. sj in addition to 0.55 ui of dj +rj. 8. jitter frequency = 5 mhz. 9. jitter frequency = 10 mhz. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 18 ta bl e 2 6 : rocketio transmitter switching characteristics description symbol conditions min typ max units serial data rate, -10 f gtx 0.622 3.125 gb/s serial data rate, -11 f gtx 0.622 6.5 gb/s data rate (gb/s) tx jitter generation (3) tj prbs7 6.5 0.50 ui (1) rj 0.35 dj 0.30 tj prbs7 5.0 0.45 rj 0.30 dj 0.25 tj prbs7 4.25 0.40 rj 0.25 dj 0.21 tj prbs7 3.125 0.28 rj 0.14 dj 0.14 tj prbs7 2.5 0.25 rj 0.18 dj 0.12 tj prbs7 1.25 0.12 rj 0.10 dj 0.06 tj prbs31 0.622 0.08 rj 0.06 dj 0.04 tx rise time (2) t rtx 20% ? 80% 90 ps tx fall time (2) t ftx 20% ? 80% 90 ps txusrclk frequency for slower speed grades = maxdatarate/32 250 mhz txusrclk2 frequency 250 mhz txusrclk duty cycle t txdc 40 60 % txusrclk2 duty cycle t tx2dc 40 60 % differential output skew t iskew 12 20 ps electrical idle transition time txoob tr a n s i t i o n 15 ns notes: 1. ui = unit interval. 2. default attributes, measured at 2.5 gb/s. 3. peak-to-peak values measured relative to 1e-12 error ra te. default attributes. tx feedback divider (txpllndivsel) = 10. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 19 iob pad input/output/3-stat e switching characteristics ta bl e 2 7 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay var- ies depending on the capab ility of the selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capa- bility of the output buffer. ta b l e 2 8 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 2 7 : iob switching characteristics (1,2) iostandard attribute (1) t iopi t ioop t iotp units speed grade speed grade speed grade -12 -11 -10 -12 -11 -10 -12 -11 -10 lvds_25 1.00 1.15 1.28 1.61 1.71 1.85 1.61 1.71 1.85 ns rsds_25 1.00 1.15 1.28 1.61 1.71 1.85 1.61 1.71 1.85 ns lvdsext_25 1.01 1.16 1.30 1.65 1.75 1.91 1.65 1.75 1.91 ns ldt_25 1.00 1.15 1.28 1.58 1.68 1.82 1.58 1.68 1.82 ns blvds_25 1.00 1.15 1.28 1.99 2.15 2.34 1.99 2.15 2.34 ns ulvds_25 1.00 1.15 1.28 1.59 1.68 1.83 1.59 1.68 1.83 ns pci33_3 (pci, 33 mhz, 3.3v) 0.76 0.87 0.97 2.52 2.76 3.02 2.52 2.76 3.02 ns pci66_3 (pci, 66 mhz, 3.3v) 0.76 0.87 0.97 2.22 2.46 2.72 2.22 2.46 2.72 ns pci-x 0.76 0.87 0.97 2.19 2.21 2.25 2.19 2.21 2.25 ns gtl 1.28 1.47 1.63 1.75 1.87 2.03 1.75 1.87 2.03 ns gtlp 1.31 1.51 1.68 1.75 1. 87 2.03 1.75 1.87 2.03 ns hstl_i 1.28 1.47 1.64 2.00 2.16 2.35 2.00 2.16 2.35 ns hstl_ii 1.28 1.47 1.64 1.83 1.96 2.13 1.83 1.96 2.13 ns hstl_iii 1.28 1.47 1.64 1.90 2.04 2.22 1.90 2.04 2.22 ns hstl_iv 1.28 1.47 1.64 1.75 1.87 2.03 1.75 1.87 2.03 ns hstl_i _18 1.26 1.44 1.60 1. 89 2.03 2.21 1.89 2.03 2.21 ns hstl_ii _18 1.26 1.44 1.60 1.85 1.98 2.16 1.85 1.98 2.16 ns hstl_iii _18 1.26 1.44 1.60 1. 80 1.93 2.09 1.80 1.93 2.09 ns hstl_iv_18 1.26 1.44 1.60 1. 77 1.89 2.06 1.77 1.89 2.06 ns sstl2_i 1.31 1.51 1.68 2.06 2.23 2.43 2.06 2.23 2.43 ns sstl2_ii 1.31 1.51 1.68 1.85 1.98 2.16 1.85 1.98 2.16 ns lvttl, slow, 2 ma 0.76 0.87 0.97 5.66 6.37 7.03 5.66 6.37 7.03 ns lvttl, slow, 4 ma 0.76 0.87 0.97 4.10 4.57 5.04 4.10 4.57 5.04 ns lvttl, slow, 6 ma 0.76 0.87 0.97 4.00 4.46 4.91 4.00 4.46 4.91 ns lvttl, slow, 8 ma 0.76 0.87 0.97 4.00 4.46 4.91 4.00 4.46 4.91 ns virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 20 lvttl, slow, 12 ma 0.76 0.87 0. 97 3.26 3.61 3.96 3.26 3.61 3.96 ns lvttl, slow, 16 ma 0.76 0.87 0. 97 2.87 3.16 3.46 2.87 3.16 3.46 ns lvttl, slow, 24 ma 0.76 0.87 0. 97 2.60 2.85 3.12 2.60 2.85 3.12 ns lvttl, fast, 2 ma 0.76 0.87 0.97 3.96 4.41 4.86 3.96 4.41 4.86 ns lvttl, fast, 4 ma 0.76 0.87 0.97 2.87 3.16 3.46 2.87 3.16 3.46 ns lvttl, fast, 6 ma 0.76 0.87 0.97 2.51 2.74 3.00 2.51 2.74 3.00 ns lvttl, fast, 8 ma 0.76 0.87 0.97 2.34 2.55 2.79 2.34 2.55 2.79 ns lvttl, fast, 12 ma 0.76 0.87 0. 97 2.09 2.26 2.47 2.09 2.26 2.47 ns lvttl, fast, 16 ma 0.76 0.87 0. 97 2.09 2.26 2.47 2.09 2.26 2.47 ns lvttl, fast, 24 ma 0.76 0.87 0. 97 1.88 2.02 2.20 1.88 2.02 2.20 ns lvcmos33, slow, 2 ma 0.76 0.87 0.9 7 6.98 7.88 8.73 6.98 7.88 8.73 ns lvcmos33, slow, 4 ma 0.76 0.87 0.9 7 4.92 5.52 6.09 4.92 5.52 6.09 ns lvcmos33, slow, 6 ma 0.76 0.87 0.9 7 4.07 4.54 5.00 4.07 4.54 5.00 ns lvcmos33, slow, 8 ma 0.76 0.87 0.9 7 3.25 3.59 3.95 3.25 3.59 3.95 ns lvcmos33, slow, 12 ma 0.76 0.87 0. 97 2.83 3.11 3.42 2.83 3.11 3.42 ns lvcmos33, slow, 16 ma 0.76 0.87 0. 97 2.11 2.28 2.49 2.11 2.28 2.49 ns lvcmos33, slow, 24 ma 0.76 0.87 0. 97 2.11 2.28 2.49 2.11 2.28 2.49 ns lvcmos33, fast, 2 ma 0.76 0.87 0.97 5.98 6.73 7.44 5.98 6.73 7.44 ns lvcmos33, fast, 4 ma 0.76 0.87 0.97 3.55 3.93 4.33 3.55 3.93 4.33 ns lvcmos33, fast, 6 ma 0.76 0.87 0.97 2.93 3.23 3.55 2.93 3.23 3.55 ns lvcmos33, fast, 8 ma 0.76 0.87 0.97 2.09 2.25 2.46 2.09 2.25 2.46 ns lvcmos33, fast, 12 ma 0.76 0.87 0. 97 1.93 2.08 2.27 1.93 2.08 2.27 ns lvcmos33, fast, 16 ma 0.76 0.87 0. 97 1.79 1.91 2.08 1.79 1.91 2.08 ns lvcmos33, fast, 24 ma 0.76 0.87 0. 97 1.79 1.91 2.08 1.79 1.91 2.08 ns lvcmos25, slow, 2 ma 0.69 0.80 0.8 8 4.77 5.34 5.89 4.77 5.34 5.89 ns lvcmos25, slow, 4 ma 0.69 0.80 0.8 8 4.09 4.56 5.02 4.09 4.56 5.02 ns lvcmos25, slow, 6 ma 0.69 0.80 0.8 8 3.53 3.92 4.31 3.53 3.92 4.31 ns lvcmos25, slow, 8 ma 0.69 0.80 0.8 8 3.53 3.92 4.31 3.53 3.92 4.31 ns lvcmos25, slow, 12 ma 0.69 0.80 0. 88 2.90 3.19 3.50 2.90 3.19 3.50 ns lvcmos25, slow, 16 ma 0.69 0.80 0. 88 2.75 3.02 3.31 2.75 2.02 3.31 ns lvcmos25, slow, 24 ma 0.69 0.80 0. 88 2.33 2.54 2.77 2.33 2.54 2.77 ns lvcmos25, fast, 2 ma 0.69 0.80 0.88 3.20 3.54 3.89 3.20 3.54 3.89 ns lvcmos25, fast, 4 ma 0.69 0.80 0.88 2.66 2.92 3.19 2.66 2.92 3.19 ns lvcmos25, fast, 6 ma 0.69 0.80 0.88 2.36 2.57 2.81 2.36 2.57 2.81 ns lvcmos25, fast, 8 ma 0.69 0.80 0.88 2.13 2.31 2.52 2.13 2.31 2.52 ns lvcmos25, fast, 12 ma 0.69 0.80 0. 88 2.06 2.23 2.43 2.06 2.23 2.43 ns ta bl e 2 7 : iob switching characteristics (1,2) (continued) iostandard attribute (1) t iopi t ioop t iotp units speed grade speed grade speed grade -12 -11 -10 -12 -11 -10 -12 -11 -10 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 21 lvcmos25, fast, 16 ma 0.69 0.80 0. 88 1.89 2.03 2.21 1.89 2.03 2.21 ns lvcmos25, fast, 24 ma 0.69 0.80 0. 88 1.83 1.96 2.13 1.83 1.96 2.13 ns lvcmos18, slow, 2 ma 0.97 1.12 1.2 5 4.77 5.34 5.89 4.77 5.34 5.89 ns lvcmos18, slow, 4 ma 0.97 1.12 1.2 5 3.56 3.95 4.35 3.56 3.95 4.35 ns lvcmos18, slow, 6 ma 0.97 1.12 1.2 5 3.29 3.64 4.00 3.29 3.64 4.00 ns lvcmos18, slow, 8 ma 0.97 1.12 1.2 5 3.10 3.42 3.76 3.10 3.42 3.76 ns lvcmos18, slow, 12 ma 0.97 1.12 1. 25 3.09 3.41 3.74 3.09 3.41 3.74 ns lvcmos18, slow, 16 ma 0.97 1.12 1. 25 2.94 3.24 3.55 2.94 3.24 3.55 ns lvcmos18, fast, 2 ma 0.97 1.12 1.25 3.20 3.54 3.89 3.20 3.54 3.89 ns lvcmos18, fast, 4 ma 0.97 1.12 1.25 2.52 2.75 3.02 2.52 2.75 3.02 ns lvcmos18, fast, 6 ma 0.97 1.12 1.25 2.29 2.49 2.72 2.29 2.49 2.72 ns lvcmos18, fast, 8 ma 0.97 1.12 1.25 2.13 2.31 2.52 2.13 2.31 2.52 ns lvcmos18, fast, 12 ma 0.97 1.12 1. 25 2.01 2.17 2.36 2.01 2.17 2.36 ns lvcmos18, fast, 16 ma 0.97 1.12 1. 25 1.94 2.09 2.27 1.94 2.09 2.27 ns lvcmos15, slow, 2 ma 1.05 1.20 1.3 4 5.33 5.99 6.61 5.33 5.99 6.61 ns lvcmos15, slow, 4 ma 1.05 1.20 1.3 4 4.21 4.70 4.88 4.21 4.70 4.88 ns lvcmos15, slow, 6 ma 1.05 1.20 1.3 4 3.49 3.87 4.26 3.49 3.87 4.26 ns lvcmos15, slow, 8 ma 1.05 1.20 1.3 4 3.49 3.87 4.26 3.49 3.87 4.26 ns lvcmos15, slow, 12 ma 1.05 1.20 1. 34 3.11 3.43 3.77 3.11 3.43 3.77 ns lvcmos15, slow, 16 ma 1.05 1.20 1. 34 2.92 3.21 3.53 2.92 3.21 3.53 ns lvcmos15, fast, 2 ma 1.05 1.20 1.34 3.42 3.79 4.17 3.42 3.79 4.17 ns lvcmos15, fast, 4 ma 1.05 1.20 1.34 2.76 3.03 3.32 2.76 3.03 3.32 ns lvcmos15, fast, 6 ma 1.05 1.20 1.34 2.46 2.69 2.94 2.46 2.69 2.94 ns lvcmos15, fast, 8 ma 1.05 1.20 1.34 2.28 2.48 2.71 2.28 2.48 2.71 ns lvcmos15, fast, 12 ma 1.05 1.20 1. 34 2.12 2.29 2.50 2.12 2.29 2.50 ns lvcmos15, fast, 16 ma 1.05 1.20 1. 34 2.06 2.23 2.43 2.06 2.23 2.43 ns lvdci_33 0.76 0.87 0.97 2.61 2.86 3.13 2.61 2.86 3.13 ns lvdci_25 0.69 0.80 0.88 2.52 2.76 3.02 2.52 2.76 3.02 ns lvdci_18 0.97 1.12 1.25 2.47 2.69 2.95 2.47 2.69 2.95 ns lvdci_15 1.05 1.20 1.34 2.45 2.68 2.93 2.45 2.68 2.93 ns lvdci_dv2_25 0.69 0.80 0.88 1.93 2.08 2.27 1.93 2.08 2.27 ns lvdci_dv2_18 0.97 1.12 1.25 1.95 2.09 2.28 1.95 2.09 2.28 ns lvdci_dv2_15 1.05 1.20 1.34 2.18 2.36 2.58 2.18 2.36 2.58 ns gtl_dci (3) 1.18 1.36 1.51 1.75 1.87 2.03 1.75 1.87 2.03 ns gtlp_dci (3) 0.96 1.11 1.23 1.75 1.87 2.03 1.75 1.87 2.03 ns hstl_i_dci (3) 1.28 1.47 1.64 2.00 2.16 2.35 2.00 2.16 2.35 ns ta bl e 2 7 : iob switching characteristics (1,2) (continued) iostandard attribute (1) t iopi t ioop t iotp units speed grade speed grade speed grade -12 -11 -10 -12 -11 -10 -12 -11 -10 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 22 ethernet mac switch ing characteristics consult ug074 : virtex-4 fpga embedded tri-mode ethernet mac user guide for further information. hstl_ii_dci (3) 1.28 1.47 1.64 1.83 1.96 2.13 1.83 1.96 2.13 ns hstl_iii_dci (3) 1.28 1.47 1.64 1.90 2.04 2.22 1.90 2.04 2.22 ns hstl_iv_dci (3) 1.28 1.47 1.64 1.75 1.87 2.03 1.75 1.87 2.03 ns hstl_i_dci_18 (3) 1.26 1.44 1.60 1.89 2.03 2.21 1.89 2.03 2.21 ns hstl_ii_dci_18 (3) 1.26 1.44 1.60 1.85 1.98 2.16 1.85 1.98 2.16 ns hstl_iii_dci_18 (3) 1.26 1.44 1.60 1.80 1.93 2.09 1.80 1.93 2.09 ns hstl_iv_dci_18 (3) 1.26 1.44 1.60 1.77 1.89 2.06 1.77 1.89 2.06 ns sstl2_i_dci (3) 1.31 1.51 1.68 2.09 2.25 2.46 2.09 2.25 2.46 ns sstl2_ii_dci (3) 1.31 1.51 1.68 2.07 2.24 2.45 2.07 2.24 2.45 ns lvpecl_25 1.38 1.59 1.77 1.52 1.61 1.74 1.52 1.61 1.74 ns sstl18_i 1.31 1.51 1.68 2.15 2.33 2.54 2.15 2.33 2.54 ns sstl18_ii 1.31 1.51 1.68 1.92 2.06 2.24 1.92 2.06 2.24 ns sstl18_i_dci (3) 1.31 1.51 1.68 1.97 2.12 2.32 1.97 2.12 2.32 ns sstl18_ii_dci (3) 1.31 1.51 1.68 1.87 2.00 2.18 1.87 2.00 2.18 ns notes: 1. the i/o standard is selected in the xilinx i se? software tool using the iostandard attribute. 2. all i/o timing specificati ons are measured with v cco at ?5% from nominal. 3. the values of the dci reference resistors must be within a 20 ?100 range. refer to ug070 , virtex-4 fpga user guide , for detailed information. ta bl e 2 7 : iob switching characteristics (1,2) (continued) iostandard attribute (1) t iopi t ioop t iotp units speed grade speed grade speed grade -12 -11 -10 -12 -11 -10 -12 -11 -10 ta bl e 2 8 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -12 -11 -10 t iotphz t input to pad high-impedance 0.88 1.01 1.12 ns ta bl e 2 9 : maximum ethernet mac performance description speed grade units -12 -11 -10 ethernet mac maximum performance 10/100/1000 mb/s virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 23 i/o standard adjustment measurement methodology input delay measurements ta bl e 3 0 shows the test setup parameters used for measuring input delay. ta bl e 3 0 : input delay measurement methodology description i /o standard attribute v l (1,2) v h (1,2) v meas (1,4,5) v ref (1,3,5) lvttl (low-voltage transistor-transistor logic) lvttl 0 3.0 1.4 ? lvcmos (low-voltage cmos), 3.3v lvcmos33 0 3.3 1.65 ? lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? pci (peripheral component interface), 33 mhz, 3.3v pci33_3 per pci? specification ? pci, 66 mhz, 3.3v pci66_3 per pci specification ? pci-x, 133 mhz, 3.3v pcix pe r pci-x? specification ? gtl (gunning transceiver logic) gtl v ref ?0.2 v ref +0.2 v ref 0.80 gtl plus gtlp v ref ?0.2 v ref +0.2 v ref 1.0 hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii & iv hstl_iii, hstl_iv v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii & iv, 1.8v hstl_iii_18, hstl_iv_18 v ref ?0.5 v ref +0.5 v ref 1.08 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?1.00 v ref +1.00 v ref 1.5 sstl, class i & ii, 2.5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 agp-2x/agp (accelerated graphics port) agp v ref ? (0.2 xv cco ) v ref + (0.2 xv cco ) v ref agp spec lvds (low-voltage differential signali ng), 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 1.2 lvdsext (lvds extended mode), 2. 5v lvdsext_25 1.2 ? 0.125 1.2 + 0.125 1.2 ulvds (ultra lvds), 2.5v ul vds_25 0.6 ? 0.125 0.6 + 0.125 0.6 ldt (hypertransport), 2.5v ldt_25 0.6 ? 0.125 0.6 + 0.125 0.6 notes: 1. input delay measurement methodology parameters for lvdci and hslv dci are the same as for lvcmos standards of the same voltage . parameters for all other dci standards are t he same as for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect wors t case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 4 . virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 24 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4 inches of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4 inch trace is char- acterized separately and subtracted from the final measure- ment, and is therefore not included in the generalized test setup shown in figure 4 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parame- ters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate predic- tion of propagation delay in any given application can be obtained through ibis simu lation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 3 1 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual worst-case propagation delay (clock-to-input) of the pcb trace. figure 4: generalized test setup v ref r ref v meas (voltage level when taking delay measurement) c ref (probe capacitance) fpga output ds302_05_031708 ta bl e 3 1 : output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvttl (low-voltage transistor-transistor logic) lvttl (all) 1m 0 1.4 0 lvcmos (low-voltage cmos), 3.3v lvcmos33 1m 0 1.65 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.75 0 pci (peripheral component interface), 33 mhz, 3.3v pci33_3 (rising edge) 25 10 (2) 0.94 0 pci33_3 (falling edge) 25 10 (2) 2.03 3.3 pci, 66 mhz, 3.3v pci66_3 (rising edge) 25 10 (2) 0.94 0 pci66_3 (falling edge) 25 10 (2) 2.03 3.3 pci-x, 133 mhz, 3.3v pcix (rising edge) 25 10 (3) 0.94 pcix (falling edge 25 10 (3) 2.03 3.3 gtl (gunning transceiver logic) gtl 25 0 0.8 1.2 gtl plus gtlp 25 0 1.0 1.5 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5 hstl, class iv hstl_iv 25 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 25 hstl, class iv, 1.8v hstl_iv_18 25 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25 sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 lvds (low-voltage differential signaling), 2.5v lvds_25 50 0 v ref 1.2 lvdsext (lvds extended mode), 2.5v lvdsext_25 50 0 v ref 1.2 blvds (bus lvds), 2.5v blvds_25 1m 0 1.2 0 ldt (hypertransport), 2.5v ldt_25 50 0 v ref 0.6 lvpecl (low-voltage positi ve emitter-coupled logic), 2.5v lvpecl_25 1m 0 0.90 0 lvdci/hslvdci (low-voltage digitally controlled impedance), 3.3v lvdci_33, hslvdci_33 1m 0 1.65 0 lvdci/hslvdci, 2.5v lvdci_25, hslvdci_25 1m 0 1.25 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0 hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class iii & iv, with dci hstl_iii_dci, hstl_iv_dci 50 0 0.9 1.5 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 hstl, class iii & iv, 1.8v, with dci hstl_iii_dci_18, hstl_iv_dci_18 50 0 1.1 1.8 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl, class i & ii, 2.5v, with dci sstl2_i_dci, sstl2_ii_dci 50 0 v ref 1.25 gtl (gunning transceiver logic) with dci gtl_dci 50 0 0.8 1.2 gtl plus with dci gtlp_dci 50 0 1.0 1.5 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. per pci specifications. 3. per pci-x specifications. ta bl e 3 1 : output delay measurement methodology (continued) description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 26 input/output logic swit ching characteristics ta bl e 3 2 : ilogic switching characteristics symbol description speed grade units -12 -11 -10 setup/hold t ice1ck / t ickce1 ce1 pin setup/hold with respect to clk 0.58 ?0.23 0.66 ?0.23 0.79 ?0.23 ns t iceck / t ickce dlyce pin setup/hold with respect to c 0.16 0.11 0.19 0.13 0.23 0.16 ns t irstck / t ickrst dlyrst pin setup/hold with respect to c ?0.03 0.37 ?0.02 0.45 ?0.02 0.54 ns t iincck / t ickinc dlyinc pin setup/hold with respect to c 0.01 0.36 0.01 0.43 0.01 0.51 ns t isrck / t icksr sr/rev pin setup/hold with respect to clk 1.15 ?0.56 1.33 ?0.56 1.59 ?0.56 ns t idock / t iockd d pin setup/hold with respect to clk without delay 0.24 ?0.10 0.28 ?0.10 0.34 ?0.10 ns t idockd / t iockdd d pin setup/hold with respect to clk (iobdelay_type = default) 6.64 ?5.99 7.63 ?5.99 8.84 ?5.99 ns d pin setup/hold with respect to clk (iobdelay_type = fixed, iobdelay_value = 0) (1) 0.81 ?0.63 0.87 ?0.63 1.09 ?0.63 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.17 0.20 0.24 ns t idid d pin to o pin propagation delay (iobdelay_type = default) 6.00 6.91 7.96 ns d pin to o pin propagation delay (iobdelay_type = fixed, iobdelay_value = 0) (1) 0.74 0.79 0.99 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.50 0.59 0.71 ns t idlod d pin to q1 pin using flip-flop as a latch (iobdelay_type = default) 6.90 7.94 9.21 ns d pin to q1 pin using flip-flop as a latch (iobdelay_type = fixed, iobdelay_value = 0) (1) 1.07 1.18 1.45 ns t ickq clk to q outputs 0.53 0.60 0.72 ns t ice1q ce1 pin to q1 using flip-flop as a latch, propagation delay 0.90 1.06 1.27 ns t rq sr/rev pin to oq/tq out 1.70 2.03 2.44 ns t gsrq global set/reset to q outputs 1.54 1.73 2.03 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.53 0.59 0.70 ns, min notes: 1. recorded at 0 tap value. refer to timing report for other values. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 27 ta bl e 3 3 : ologic switching characteristics symbol description speed grade units -12 -11 -10 setup/hold t odck / t ockd d1/d2 pins setup/hold with respect to clk 0.52 ?0.22 0.62 ?0.22 0.75 ?0.22 ns t ooceck / t ockoce oce pin setup/hold with respect to clk 0.53 ?0.33 0.64 ?0.33 0.77 ?0.33 ns t osrck / t ocksr sr/rev pin setup/hold with respect to clk 0.99 ?0.55 1.18 ?0.55 1.42 ?0.55 ns t otck / t ockt t1/t2 pins setup/hold with respect to clk 0.52 ?0.22 0.62 ?0.22 0.75 ?0.22 ns t otceck / t ocktce tce pin setup/hold with respect to clk 0.53 ?0.33 0.64 ?0.33 0.77 ?0.33 ns combinatorial t odq d1 to oq out 0.56 0.65 0.76 ns t otq t1 to tq out 0.56 0.65 0.76 ns sequential delays t iosron rev pin to tq out 1.14 1.37 1.64 ns t ockq clk to oq/tq out 0.41 0.49 0.59 ns t rq sr/rev pin to oq/tq out 1.14 1.37 1.64 ns t gsrq global set/reset to q outputs 1.54 1.73 2.03 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.53 0.59 0.70 ns, min virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 28 input serializer/deserializer switching characteristics ta bl e 3 4 : iserdes switching characteristics symbol description speed grade units -12 -11 -10 setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.28 ?0.20 0.34 ?0.16 0.40 ?0.13 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.48 ?0.37 0.57 ?0.30 0.69 ?0.25 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.11 ?0.04 0.14 ?0.03 0.16 ?0.02 ns t iscck_dlyce / t isckc_dlyce dlyce pin setup/hold with respect to clkdiv 0.16 0.11 0.19 0.13 0.23 0.16 ns t iscck_dlyinc / t isckc_dlyinc dlyinc pin setup/hold with respect to clkdiv 0.01 0.36 0.01 0.43 0.01 0.51 ns t iscck_dlyrst / t isckc_dlyrst dlyrst pin setup/hold with respect to clkdiv ?0.03 0.37 ?0.02 0.45 ?0.02 0.54 ns t iscck_sr sr pin setup with respect to clkdiv 0.64 0.77 0.92 ns setup/hold for data lines t isdck_d / t isckd_d d pin setup/hold with respect to clk (iobdelay = ibuf or none) 0.24 ?0.11 0.28 ?0.11 0.34 ?0.11 ns d pin setup/hold with respect to clk (iobdelay = ifd or both, iobdelay_type = default) 6.64 ?6.51 7.63 ?6.51 8.84 ?6.51 ns d pin setup/hold with respect to clk (1) (iobdelay = ifd or both, iobdelay_type = fixed, iobdelay_value = 0) 0.81 ?0.68 0.87 ?0.68 1.08 ?0.68 ns t isdck_ddr / t isckd_ddr d pin setup/hold with respect to clk at ddr mode (iobdelay = ibuf or none) 0.24 ?0.11 0.28 ?0.11 0.34 ?0.11 ns d pin setup/hold with respect to clk at ddr mode (iobdelay = ifd or both, iobdelay_type = default) 6.64 ?6.51 7.63 ?6.51 8.84 ?6.51 ns d pin setup/hold with respect to clk at ddr mode (1) (iobdelay = ifd or both, iobdelay_type = fixed, iobdelay_value = 0) 0.81 ?0.68 0.87 ?0.68 1.08 ?0.68 ns sequential delays t iscko_q clkdiv to out at q pin 0.59 0.71 0.85 ns propagation delays t isdo_do_iobdelay_ifd d input to do output pin (iobdelay = ifd) 0.17 0.20 0.24 ns t isdo_do_iobdelay_none d input to do output pin (i obdelay = none) 0.17 0.20 0.24 ns t isdo_do_iobdelay_both d input to do output pin (iobdelay = both, iobdelay_type = default) 6.00 6.91 7.96 ns d input to do output pin (1) (iobdelay = both, iobdelay_type = fixed, iobdelay_value = 0) 0.74 0.79 0.99 ns t isdo_do_iobdelay_ibuf d input to do output pin (iobdelay = ibuf, iobdelay_type = default) 6.00 6.91 7.96 ns d input to do output pin (1) (iobdelay = ibuf, iobdelay_type = fixed, iobdelay_value = 0) 0.74 0.79 0.99 ns notes: 1. recorded at 0 tap value. refer to timing report for other values. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce / t isckc_ce in trce report. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 29 input delay switching characteristics ta bl e 3 5 : input delay switching characteristics symbol description speed grade units -12 -11 -10 idelayctrl t idelayctrlco_rdy reset to ready for idelayctrl (maximum) 3.00 3.00 3.00 s f idelayctrl_ref refclk frequency 200 200 200 mhz idelayctrl_ref_precision (2) refclk precision 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 50.0 50.0 50.0 ns idelay t idelayresolution idelay chain delay resolution 75 75 75 ps t idelaytotal_err cumulative delay at a given tap (3) [(tap ? 1) x 75 + 34] 0.07[(tap ? 1) x 75 + 34] ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern 000 note (4) pattern dependent period jitter in delay chain for random data pattern (prbs 23) 10 2 10 2 10 2 note (4) f max c clock maximum frequency 300 250 250 mhz notes: 1. refer to xilinx application note xapp707 for details on idelay timing characteristics. 2. see the ?refclk - reference clock? se ction (specific to idelayctrl) in the virtex-4 fpga user guide : chapter 7, selectio logic resources. 3. this value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps. 4. units in ps peak-to-peak per tap. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 30 output serializer/deseriali zer switching characteristics ta bl e 3 6 : oserdes switching characteristics symbol description speed grade units -12 -11 -10 setup/hold t osdck_d / t osckd_d d input setup/hold with respect to clkdiv 0.35 ?0.05 0.42 ?0.04 0.50 ?0.03 ns t osdck_t / t osckd_t (1) t input setup/hold with respect to clk 0.43 ?0.16 0.52 ?0.16 0.62 ?0.16 ns t osdck_t2 / t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.35 ?0.05 0.42 ?0.04 0.50 ?0.03 ns t oscck_oce / t osckc_oce oce input setup/hold with respect to clk 0.45 0.01 0.53 0.02 0.64 0.03 ns t oscck_s sr (reset) input setup with re spect to clkdiv 0.67 0.80 0.96 ns t oscck_tce / t osckc_tce tce input setup/hold with respect to clk 0.45 0.01 0.53 0.02 0.64 0.03 ns sequential delays t oscko_oq clock to out from clk to oq 0.41 0.49 0.59 ns t oscko_tq clock to out from clk to tq 0.41 0.49 0.59 ns combinatorial t osdo_ttq t input to tq out 0.56 0.65 0.76 ns t osco_oq asynchronous reset to oq 1.14 1.37 1.64 ns t osco_tq asynchronous reset to tq 1.14 1.37 1.64 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t / t osckd_t in trce report. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 31 clb switching characteristics ta bl e 3 7 : clb switching characteristics symbol description speed grade units -12 -11 -10 xc4vfx (2) xc4vlx/sx all devices combinatorial delays t ilo 4-input function: f/g inputs to x/y outputs 0.15 0.15 0.17 0.20 ns, max t if5 5-input function: f/g inputs to f5 output 0.36 0.35 0.40 0.46 ns, max t if5x 5-input function: f/g inputs to x output 0.44 0.43 0.49 0.57 ns, max t if6y fxina or fxinb inputs to ymux output 0.30 0.30 0.34 0.39 ns, max t inafx fxina input to fx output via muxfx 0.21 0.21 0.23 0.27 ns, max t inbfx fxinb input to fx output via muxfx 0.21 0.20 0.23 0.26 ns, max t bxx bx input to xmux output 0.59 0.58 0.65 0.76 ns, max t byy by input to ymux output 0.43 0.43 0.48 0.56 ns, max t bxcy bx input to c out output ? getting into carry chain (3) 0.60 0.59 0.66 0.78 ns, max t bycy by input to c out output ? getting into carry chain (3) 0.49 0.48 0.54 0.63 ns, max t byp c in input to c out output ? carry chain delay (3) 0.07 0.07 0.08 0.09 ns, max t opcyf f input to c out output ? getting out from carry chain (3) 0.45 0.44 0.50 0.58 ns, max t opcyg g input to c out output ? getting out from carry chain (3) 0.44 0.43 0.48 0.57 ns, max sequential delays t cko ff clock clk to xq/yq outputs 0.28 0.28 0.31 0.36 ns, max t cklo latch clock clk to xq/yq outputs 0.37 0.36 0.41 0.48 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick / t ckdi bx/by inputs 0.36 ?0.09 0.36 ?0.09 0.40 ?0.09 0.47 ?0.09 ns, min t ceck / t ckce ce input 0.58 ?0.16 0.57 ?0.16 0.64 ?0.16 0.75 ?0.16 ns, min t fxck / t ckfx fxina/fxinb inputs 0.42 ?0.14 0.41 ?0.14 0.46 ?0.14 0.54 ?0.14 ns, min t srck / t cksr sr/by inputs (synchronous) 1.04 ?0.74 1.02 ?0.73 1.15 ?0.73 1.35 ?0.73 ns, min t cinck / t ckcin c in data inputs (di) ? getting out from carry chain (3) 0.52 ?0.23 0.51 ?0.23 0.57 ?0.23 0.67 ?0.23 ns, min set/reset t rpw minimum pulse width, sr/by inputs 0.54 0.53 0.59 0.70 ns, min t rq delay from sr/by inpu ts to xq/yq outputs (asynchronous) 1.05 1.03 1.15 1.35 ns, max f tog toggle frequency (mhz) (for export control) 1181 1205 1205 (4) 1028 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. the values in this column apply to all xc4vfx -12 parts except xc4vfx12 -12. for xc4vfx12 -12 values, use the values in the adjacent 4vlx/sx -12 column. 3. these items are of interest for carry chain applications. 4. xc4vfx -11 devices are 1181 mhz. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 32 clb distributed ram switching characteristics (slicem only) ) clb shift register switching characteristics (slicem only) ) ta bl e 3 8 : clb distributed ram swit ching characteristics symbol description speed grade units -12 -11 -10 xc4vfx (2) xc4vlx/sx all devices sequential delays t shcko clock clk to x outputs (we active) (3) 1.61 1.58 1.77 2.08 ns, max t shckof5 clock clk to f5 output (we active) 1.53 1.50 1.69 1.98 ns, max setup and hold times before/after clock clk t ds / t dh bx/by data inputs (di) 1.26 ?0.90 1.23 ?0.88 1.46 ?0.88 1.80 ?0.88 ns, min t as / t ah f/g address inputs 0.88 ?0.37 0.86 ?0.37 0.97 ?0.34 1.13 ?0.29 ns, min t ws / t wh we input (sr) 1.10 ?0.48 1.08 ?0.47 1.21 ?0.47 1.42 ?0.47 ns, min clock clk t wph minimum pulse width, high 0.53 0.52 0.59 0.69 ns, min t wpl minimum pulse width, low 0.55 0.54 0.60 0.70 ns, min t wc minimum clock period to meet address write cycle time 0.76 0.74 0.84 0.98 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. the values in this column apply to all xc4vfx -12 parts except xc4vfx12 -12. for xc4vfx12 -12 val ues, use the values in the adjacent xc4vlx/sx -12 column. 3. t shcko also represents the clk to xmux output. refer to trce report for the clk to xmux path. ta bl e 3 9 : clb shift register swit ching characteristics symbol description speed grade units -12 -11 -10 xc4vfx (2) xc4vlx/sx xc4vfx (3) xc4vlx/sx all sequential delays t reg clock clk to x/y outputs 2.12 2.08 2.19 2.19 2.57 ns, max t regxb clock clk to xb output via mc15 lut output 1.83 1.73 1.90 1.84 2.16 ns, max t regyb clock clk to yb output via mc15 lut output 1.84 1.74 1.92 1.85 2.17 ns, max t cksh clock clk to shiftout 1.70 1.60 1.76 1.70 1.99 ns, max t regf5 clock clk to f5 output 2.05 2.01 2.11 2.11 2.47 ns, max setup and hold times before/after clock clk t ws / t wh we input (sr) 0.87 ?0.76 0.85 ?0.76 0.96 ?0.70 0.96 ?0.70 1.12 ?0.62 ns, min t ds / t dh bx/by data inputs (di) 1.28 ?1.12 1.25 ?1.11 1.45 ?1.11 1.45 ?1.11 1.75 ?1.11 ns, min clock clk t wph minimum pulse width, high 0.53 0.52 0.59 0.59 0.69 ns, min t wpl minimum pulse width, low 0.55 0.54 0.60 0.60 0.70 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. the values in this column apply to all xc4vfx -12 parts except xc4vfx12 -12. for xc4vfx12 -12 val ues, use the values in the adjacent xc4vlx/sx -12 column. 3. the values in this column apply to all xc4vfx -11 parts. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 33 block ram and fifo swit ching characteristics ta bl e 4 0 : block ram switching characteristics symbol description speed grade units -12 -11 -10 sequential delays t rcko_dora clock clk to dout output (without output register) (2) 1.65 1.83 2.10 ns, max clock clk to dout output with ecc (without output register) 3.00 3.33 3.83 ns, max t rcko_doa clock clk to dout output (with output register) (3) 0.72 0.80 0.92 ns, max clock clk to dout output with ecc (with output register) 2.00 2.20 2.50 ns, max setup and hold tim es before clock clk t rcck_addr / t rckc_addr addr inputs 0.34 0.26 0.37 0.28 0.43 0.33 ns, min t rdck_di / t rckd_di din inputs (4) 0.18 0.26 0.20 0.28 0.23 0.33 ns, min t rcck_en / t rckc_en en input (5) 0.41 0.26 0.45 0.28 0.52 0.33 ns, min t rcck_regce / t rckc_regce ce input of output register 0.25 0.26 0.27 0.28 0.32 0.33 ns, min t rcck_ssr / t rckc_ssr rst input 0.25 0.26 0.27 0.28 0.32 0.33 ns, min t rcck_we / t rckc_we wen input 0.59 0.26 0.65 0.28 0.75 0.33 ns, min maximum frequency f max write first and no change mode 500.00 450.45 400.00 mhz f max read first mode 500.00 450.45 400.00 mhz clk-to-clk read first mode 500.00 450.45 400.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. t rcko_dora includes t rcko_dowa , t rcko_dopar , and t rcko_dopaw as well as the b port equivalent timing parameters. 3. t rcko_doa includes t rcko_dopa as well as the b port equi valent timing parameters. 4. t rcko_di includes both a and b inputs as well as the parity inputs of a and b. 5. xilinx block rams do not have asynchr onous inputs on an enabled port address. during th e time that a port is enabled, its add resses must be stable during the specified set-up time. do not creat e an asynchronous input on an enabled port address. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 34 ta bl e 4 1 : fifo switching characteristics symbol description speed grade units -12 -11 -10 sequential delays t fcko_do clock clk to do output (2) 0.72 0.80 0.92 ns, max t fcko_flags clock clk to fifo flags outputs (3) 0.93 1.04 1.19 ns, max t fcko_pointers clock clk to fifo pointer outputs (4) 1.16 1.29 1.48 ns, max setup and hold tim es before clock clk t fdck_di / t fckd_di di input (5) 0.18 0.26 0.20 0.28 0.23 0.33 ns, min t fcck_en / t fckc_en enable inputs (6) 0.66 0.26 0.73 0.28 0.84 0.33 ns, min reset delays t fco_flags reset rst to flags (7) 1.32 1.46 1.68 ns, max maximum frequency f max fifo in all modes 500.00 450.45 400.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. t fcko_do includes parity output (t fcko_dop ). 3. t fcko_flags includes the following parameters: t fcko_aempty , t fcko_afull , t fcko_empty , t fcko_full , t fcko_rderr , t fcko_wrerr. 4. t fcko_pointers includes both t fcko_rdcount and t fcko_wrcount. 5. t fdck_di includes parity inputs (t fdck_dip ). 6. t fcck_en includes both write and read enable. 7. t fco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrerr, rdcount and wrcount. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 35 xtremedsp? switch ing characteristics ta bl e 4 2 : xtremedsp switchin g characteristics symbol description speed grade units -12 -11 -10 setup and hold of ce pins t dspcck_ce / t dspckc_ce setup/hold of all ce inputs of the dsp48 slice 0.39 0.09 0.43 0.10 0.49 0.12 ns t dspcck_rst / t dspckc_rst setup/hold of all rst inputs of the dsp48 slice 0.32 0.09 0.36 0.10 0.40 0.12 ns setup and hold times of data t dspdck_{aa, bb, cc} / t dspckd_{aa, bb, cc} setup/hold of {a, b, c} in put to {a, b, c} register 0.25 0.23 0.28 0.26 0.32 0.29 ns t dspdck_{am, bm} / t dspckd_{am, bm} setup/hold of {a, b} input to m register 1.82 0.00 2.03 0.00 2.28 0.00 ns sequential delays t dspcko_pp clock to out from p register to p output 0.64 0.71 0.79 ns t dspcko_pm clock to out from m register to p output 2.38 2.65 2.98 ns combinatorial t dspdo_{ap, bp}l {a, b} input to p output (legacy_mode = mult18x18) 3.53 3.92 4.41 ns maximum frequency f max from {a, b} register to p register (legacy_mode = mult18x18) 317.46 285.71 253.94 mhz fully pipelined 500.00 450.05 400.00 mhz virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 36 configuration switch ing characteristics ta bl e 4 3 : configuration switching characteristics symbol description speed grade units -12 -11 -10 power-up timing characteristics t config (1,2) maximum time to configure device after v ccint has been applied. 10 10 10 minutes t pl program latency 0.5 0.5 0.5 s/frame, max t por power-on-reset t pl +10 t pl +10 t pl +10 ms, max t icck cclk (output) delay 500 500 500 ns, min t program program pulse width 300 300 300 ns, min master/slave serial mode programming switching t dcc / t ccd din setup/hold, slave mode 0.5 1.0 0.5 1.0 0.5 1.0 ns, min t dsck / t sckd din setup/hold, master mode 0.5 1.0 0.5 1.0 0.5 1.0 ns, min t cco dout 7.5 7.5 7.5 ns, max t cch high time 2.0 2.0 2.0 ns, min t ccl low time 2.0 2.0 2.0 ns, min f cc_serial maximum frequency, master mode with respect to nominal cclk. 100 100 100 mhz, max f max_slave / f max_icap maximum frequency, slave mode external cclk 100 100 100 mhz, max f mcctol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 % selectmap mode programming switching t smdcc / t smccd selectmap data setup/hold 2.0 0.0 2.0 0.0 2.0 0.0 ns, min t smcscc / t smcccs cs_b setup/hold 1.0 0.5 1.0 0.5 1.0 0.5 ns, min t smccw / t smwcc rdwr_b setup/hold 6.0 1.0 6.0 1.0 6.0 1.0 ns, min t smckby busy propagation delay 8.0 8.0 8.0 ns, max f cc_selectmap maximum frequency, master mode with respect to nominal cclk. 100 100 100 mhz, max f max_selectmap maximum configuration frequency, slave mode external cclk 100 100 100 mhz, max f max_readback maximum readback frequency 80 80 80 mhz, max f mcctol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 % t smco selectmap readback clock-to-out 8.0 8.0 8.0 ns, max virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 37 boundary-scan port timing specifications t taptck tms and tdi setup time before tck 1.0 1.0 1.0 ns, min t tcktap tms and tdi hold time after tck 2.0 2.0 2.0 ns, min t tcktdo tck falling edge to tdo output valid 6.0 6.0 6.0 ns, max f tck maximum configuration tck clock frequency 66 66 66 mhz, max f tckb maximum boundary-scan tck clock frequency 50 50 50 mhz, max dynamic reconfiguration port (drp) for dcm clkin_freq_dll_hf_ms_max maximum frequency for dclk 500 450 400 mhz, max t dmcck_daddr /t dmckc_daddr daddr setup/hold time 0.54 0.00 0.63 0.00 0.72 0.00 ns, max t dmcck_di /t dmckc_di di setup/hold time 0.54 0.00 0.63 0.00 0.72 0.00 ns, max t dmcck_den /t dmckc_den den setup/hold time 0.58 0.00 0.58 0.00 0.58 0.00 ns, max t dmcck_dwe /t dmckc_dwe dwe setup/hold time 0.58 0.00 0.58 0.00 0.58 0.00 ns, max t dmcko_do clk to out of do (2) 000ns, max t dmcko_drdy clk to out of drdy 0.68 0.80 0.92 ns, max notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of t he global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glit ch-free operation. the other global clock setup and hold times a re optional; only needing to be satisfied if device operation requires simulation matches on a cycle-fo r-cycle basis when switching between clock s. 2. do holds until the next drp operation. ta bl e 4 3 : configuration switching characteristics (continued) symbol description speed grade units -12 -11 -10 virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 38 clock buffers and networks dcm and pmcd switching characteristics ta bl e 4 4 : global clock switching characteristics (including bufgctrl) symbol description speed grade units -12 -11 -10 t bccck_ce / t bcckc_ce (1) ce pins setup/hold 0.27 0.00 0.31 0.00 0.35 0.00 ns t bccck_s / t bcckc_s (1) s pins setup/hold 0.27 0.00 0.31 0.00 0.35 0.00 ns t bccko_o bufgctrl delay 0.70 0.77 0.90 ns maximum frequency f max global clock tree 500 450 400 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of t he global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glit ch-free operation. the other global clock setup and hold times a re optional; only needing to be satisfied if device operation requires simulation matches on a cycle-fo r-cycle basis when switching between clock s. ta bl e 4 5 : operating frequency ranges for dcm in maximum speed (ms) mode symbol description speed grade units -12 -11 -10 outputs clocks (low frequency mode) clkout_freq_1x_lf_ms_min clk0, clk90, clk180, clk270 32 32 32 mhz clkout_freq_1x_lf_ms_max 150 150 150 mhz clkout_freq_2x_lf_ms_min clk2x, clk2x180 64 64 64 mhz clkout_freq_2x_lf_ms_max 300 300 300 mhz clkout_freq_dv_lf_ms_min clkdv 222mhz clkout_freq_dv_lf_ms_max 100 100 100 mhz clkout_freq_fx_lf_ms_min clkfx, clkfx180 32 32 32 mhz clkout_freq_fx_lf_ms_max 210 210 210 mhz input clocks (low frequency mode) clkin_freq_dll_lf_ms_min clkin (using dll outputs) (1,3,4,5,6) 32 32 32 mhz clkin_freq_dll_lf_ms_max 150 150 150 mhz clkin_freq_fx_lf_ms_min clkin (using dfs outputs only) (2,3,4) 111mhz clkin_freq_fx_lf_ms_max 210 210 210 mhz psclk_freq_lf_ms_min psclk 111khz psclk_freq_lf_ms_max 500 450 400 mhz outputs clocks (high frequency mode) clkout_freq_1x_hf_ms_min clk0, clk90, clk180, clk270 150 150 150 mhz clkout_freq_1x_hf_ms_max 500 450 400 mhz clkout_freq_2x_hf_ms_min clk2x, clk2x180 300 300 300 mhz clkout_freq_2x_hf_ms_max 500 450 400 mhz clkout_freq_dv_hf_ms_min clkdv 9.4 9.4 9.4 mhz clkout_freq_dv_hf_ms_max 333 300 267 mhz virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 39 clkout_freq_fx_hf_ms_min clkfx, clkfx180 210 210 210 mhz clkout_freq_fx_hf_ms_max 350 315 300 mhz input clocks (high frequency mode) clkin_freq_dll_hf_ms_min (6) clkin (using dll outputs only) (1,3,4,5) 150 150 150 mhz clkin_freq_dll_hf_ms_max 500 450 400 mhz clkin_freq_fx_hf_ms_min clkin (using dfs outputs) (2,3,4) 50 50 50 mhz clkin_freq_fx_hf_ms_max (6) 350 315 300 mhz psclk_freq_hf_ms_min psclk 111khz psclk_freq_hf_ms_max 500 450 400 mhz notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by _2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45). 5. the dcm must be reset if the clock input clock stops for more than 100 ms. 6. these values also apply when using both dll and dfs outputs. ta bl e 4 5 : operating frequency ranges for dcm in maximum speed (ms) mode (continued) symbol description speed grade units -12 -11 -10 ta bl e 4 6 : operating frequency ranges for dcm in maximum range (mr) mode symbol description speed grade units -12 -11 -10 outputs clocks (low frequency mode) clkout_freq_1x_lf_mr_min clk0, clk90, clk180, clk270 19 19 19 mhz clkout_freq_1x_lf_mr_max 40 36 32 mhz clkout_freq_2x_lf_mr_min clk2x, clk2x180 38 38 38 mhz clkout_freq_2x_lf_mr_max 80 72 64 mhz clkout_freq_dv_lf_mr_min clkdv 1.2 1.2 1.2 mhz clkout_freq_dv_lf_mr_max 26.7 24 21.3 mhz clkout_freq_fx_lf_mr_min clkfx, clkfx180 19 19 19 mhz clkout_freq_fx_lf_mr_max 40 36 32 mhz input clocks (low frequency mode) clkin_freq_dll_lf_mr_min clkin (using dll outputs) (1,3,4,5,6) 19 19 19 mhz clkin_freq_dll_lf_mr_max 40 36 32 mhz clkin_freq_fx_lf_mr_min clkin (using dfs outputs only) (2,3,4) 111mhz clkin_freq_fx_lf_mr_max 35 32 28 mhz psclk_freq_lf_mr_min psclk 111khz psclk_freq_lf_mr_max 262.50 236.30 210.00 mhz notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by _2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45). 5. the dcm must be reset if the clock input clock stops for more than 100 ms. 6. these values also apply when using both dll and dfs outputs. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 40 ta bl e 4 7 : input clock tolerances symbol description frequency range value units duty cycle input tolerance (in %) clkin_psclk_pulse_range_1 psclk only < 1 mhz 25 - 75 % clkin_psclk_pulse_range_1_50 psclk and clkin 1 ? 50 mhz (1) 25 - 75 % clkin_psclk_pulse_range_50_100 50 ? 100 mhz (1) 30 - 70 % clkin_psclk_pulse_range_100_200 100 ? 200 mhz (1) 40 - 60 % clkin_psclk_pulse_range_200_400 200 ? 400 mhz (1) 45 - 55 % clkin_psclk_pulse_range_400 > 400 mhz 45 - 55 % speed grade -12 -11 -10 input clock cycle-cycle jitter (low frequency mode) clkin_cyc_jitt_dll_lf clkin (using dll outputs) (2,5,6) 300 300 345 ps clkin_cyc_jitt_fx_lf clkin (using dfs outputs) (3) 300 300 345 ps input clock cycle-cycle jitter (high frequency mode) clkin_cyc_jitt_dll_hf clkin (using dll outputs) (2,5,6) 150 150 173 ps clkin_cyc_jitt_fx_hf clkin (using dfs outputs) (3) 150 150 173 ps input clock period jitter (low frequency mode) clkin_per_jitt_dll_lf clkin (using dll outputs) (2,5,6) 1.0 1.0 1.15 ns clkin_per_jitt_fx_lf clkin (using dfs outputs) (3) 1.0 1.0 1.15 ns input clock period jitter (high frequency mode) clkin_per_jitt_dll_hf clkin (using dll outputs) (2,5,6) 1.0 1.0 1.15 ns clkin_per_jitt_fx_hf clkin (using dfs outputs) (3) 1.0 1.0 1.15 ns feedback clock path delay variation clkfb_delay_var_ext clkfb off-chip feedback 1.0 1.0 1.15 ns notes: 1. for boundary frequencies, use the more restrictive specifications. 2. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 3. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 4. if both dll and dfs outputs are used, follow the more restrictive specifications. 5. the dcm must be reset if the clock input clock stops for more than 100 ms. 6. these values also apply when using both dll and dfs outputs. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 41 output clock jitter output clock phase alignment ta bl e 4 8 : output clock jitter description symbol constraints speed grade units -12 -11 -10 clock synthesis period jitter clk0 clkout_per_jitt_0 100 100 100 ps clk90 clkout_per_jitt_90 150 150 150 ps clk180 clkout_per_jitt_180 150 150 150 ps clk270 clkout_per_jitt_270 150 150 150 ps clk2x, clk2x180 clkout_per_jitt_2x 200 200 200 ps clkdv (integer division) clkout_per_jitt_dv1 150 150 150 ps clkdv (non-integer division) clkout_per_jitt_dv2 300 300 300 ps clkfx, clkfx180 clkout _per_jitt_fx note (2) note (2) note (2) ps notes: 1. pmcd outputs are not included in this table because they do not introduce jitter. 2. values for this parameter are available from the architecture wizard. ta bl e 4 9 : output clock phase alignment description symbol constraints speed grade units -12 -11 -10 phase offset between clkin and clkfb clkin / clkfb clkin_clkfb_phase 120 120 120 ps phase offset between any dcm outputs all clk outputs clkout_phase 140 140 140 ps duty cycle precision dll outputs (1) clkout_duty_cycle_dll (3,4) 150 150 150 ps dfs outputs (2) clkout_duty_cycle_fx (4) 200 200 200 ps notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. clkout_duty_cycle_dll applies to the 1x clock outputs (clk0, clk90, clk180, and clk270) only if duty_cycle_correction=true. 4. the measured value includes the duty cycl e distortion of the global clock tree. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 42 ta bl e 5 0 : miscellaneous timing parameters symbol description speed grade units -12 -11 -10 time required to achieve lock t_lock_dll_240 dll output ? frequency range > 240 mhz (2) 20 20 20 s t_lock_dll_120_240 dll output ? frequency range 120 - 240 mhz (1,2) 63 63 63 s t_lock_dll_60_120 dll output ? frequency range 60 - 120 mhz (1,2) 225 225 225 s t_lock_dll_50_60 dll output ? frequency range 50 - 60 mhz (1,2) 325 325 325 s t_lock_dll_40_50 dll output ? frequency range 40 - 50 mhz (1,2) 500 500 500 s t_lock_dll_30_40 dll output ? frequency range 30 - 40 mhz (1,2) 900 900 900 s t_lock_dll_24_30 dll output ? frequency range 24 - 30 mhz (1,2) 1250 1250 1250 s t_lock_dll_30 dll output ? frequency range < 30 mhz (2) 1250 1250 1250 s t_lock_fx_max dfs outputs (3) 10 10 10 ms t_lock_dll_fine_shift multiplication factor for dll lock time with fine shift 2 2 2 fine phase shifting fine_shift_range_ms absolute shifting range in maximum speed mode 7 7 7 ns fine_shift_range_mr absolute shifting range in maximum range mode 10 10 10 ns delay lines dcm_tap_ms_min tap delay resolution (min) in maximum speed mode 5 5 5 ps dcm_tap_ms_max tap delay resolution (max) in maximum speed mode 40 40 40 ps dcm_tap_mr_min tap delay resolution (min) in maximum range mode 10 10 10 ps dcm_tap_mr_max tap delay resolution (max) in maximum range mode 60 60 60 ps input signal requirements dcm_reset (4) minimum duration that rst must be held asserted 200 200 200 ms maximum duration that rst can be held asserted (5) 10 10 10 sec dcm_input_clock_stop maximum duration that clkin and clkfb can be stopped (6,7) 100 100 100 ms notes: 1. for boundary frequencies, choose the higher delay. 2. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 3. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 4. clkin must be present and stable during the dcm_reset. 5. this only applies to production step 1 lx and sx devices. for t hese devices, use the design solu tions described in answer rec ord 21127 for support of longer reset durations. production step 2 lx and sx devices and all production fx devices do not have this requirement. 6. for production step 1 lx and sx devices, use the design soluti ons described in answer record 21127 for support of longer dura tions of stopped clocks. for production step 2 lx and sx devices and all production fx devices, the ise software automatically inserts a small m acro to support longer durations of stopped clocks. 7. for all stepping levels, once the input clock is toggli ng again and stable after being stopped, dcm must be reset. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 43 ta bl e 5 1 : frequency synthesis attribute min max clkfx_multiply 2 32 clkfx_divide 1 32 ta bl e 5 2 : dcm switching characteristics symbol description speed grade units -12 -11 -10 t dmcck_psen / t dmckc_psen psen setup/hold 0.93 0.00 0.93 0.00 1.07 0.00 ns t dmcck_psincdec / t dmckc_psincdec psincdec setup/hold 0.93 0.00 0.93 0.00 1.07 0.00 ns t dmcko_psdone clock to out of psdone 0.60 0.60 0.69 ns ta bl e 5 3 : pmcd switching characteristic symbol description speed grade units -12 -11 -10 t pmccck_rel / t pmcckc_rel rel setup/hold for all outputs 0.60 0.00 0.60 0.00 0.60 0.00 ns t pmcco_clk{a1,b,c,d} rst assertion to clock output deassertion 4.00 4.00 4.50 ns t pmccko_clk{a1,b,c,d} max clock propagation delay of pmcd for all outputs 4.60 4.60 5.20 ns pmcd_clk_skew max phase between all outputs assuming all inputs 150 150 150 ps clkin_freq_pmcd_clka_max (1) max input/output frequency 500 450 400 mhz clkin_psclk_pulse_range max duty cycle in put tolerance (same as dcm) note (2) pmcd_rel_high_pulse_min min pulse width for rel 1.11 1.11 1.25 ns pmcd_rst_high_pulse_min min pulse width for rst 1.11 1.11 1.25 ns notes: 1. there is no minimum frequency for pmcd. 2. refer to ta bl e 4 7 parameter: clkin_psclk_pulse_range. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 44 system-synchronous switching characteristics virtex-4 fpga pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 5 4 . values are expressed in nanoseconds unless otherwise noted. ta bl e 5 4 : global clock input to output delay for lvcmos25 standard, 12 ma, fast slew rate, with dcm symbol description device speed grade units -12 -11 -10 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm. t ickofdcm global clock and off with dcm xc4vlx15 2.43 2.81 3.25 ns xc4vlx25 2.60 2.95 3.36 ns xc4vlx40 2.54 2.91 3.32 ns xc4vlx60 2.69 3.05 3.45 ns xc4vlx80 2.88 3.27 3.72 ns xc4vlx100 2.94 3.33 3.79 ns xc4vlx160 2.94 3.35 3.82 ns xc4vlx200 n/a 3.51 4.02 ns xc4vsx25 2.65 2.99 3.39 ns xc4vsx35 2.81 3.18 3.60 ns xc4vsx55 2.83 3.20 3.62 ns xc4vfx12 2.43 2.78 3.18 ns xc4vfx20 2.54 2.88 3.26 ns xc4vfx40 2.87 3.25 3.67 ns xc4vfx60 2.92 3.31 3.77 ns xc4vfx100 3.16 3.58 4.06 ns xc4vfx140 n/a 3.79 4.30 ns notes: 1. listed above are representative values w here one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 45 ta bl e 5 5 : global clock input to output delay for lvcmos25 standard, 12 ma, fast slew rate, without dcm symbol description device speed grade units -12 -11 -10 lvcmos25 global clock input to output delay us ing output flip-flop, 12 ma, fast slew rate, without dcm. t ickof global clock and off without dcm xc4vlx15 6.42 7.22 8.14 ns xc4vlx25 6.50 7.32 8.25 ns xc4vlx40 6.70 7.54 8.50 ns xc4vlx60 6.86 7.72 8.70 ns xc4vlx80 6.98 7.85 8.85 ns xc4vlx100 7.23 8.15 9.18 ns xc4vlx160 7.46 8.40 9.46 ns xc4vlx200 n/a 8.79 9.88 ns xc4vsx25 6.69 7.52 8.47 ns xc4vsx35 6.75 7.59 8.56 ns xc4vsx55 7.10 7.99 9.00 ns xc4vfx12 6.41 7.21 8.13 ns xc4vfx20 6.60 7.42 8.37 ns xc4vfx40 6.97 7.84 8.83 ns xc4vfx60 6.98 7.86 8.85 ns xc4vfx100 7.46 8.40 9.45 ns xc4vfx140 n/a 8.80 9.90 ns notes: 1. listed above are representative values w here one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 46 virtex-4 fpga pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 5 6 . values are expressed in nanoseconds unless otherwise noted. ta bl e 5 6 : global clock setup and hold for lvcmos25 standard, with dcm symbol description device speed grade units -12 -11 -10 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcm / t phdcm no delay global clock and iff (2) with dcm xc4vlx15 1.35 ?0.72 1.52 ?0.67 1.54 ?0.62 ns xc4vlx25 1.28 ?0.58 1.50 ?0.57 1.58 ?0.55 ns xc4vlx40 1.25 ?0.55 1.44 ?0.50 1.50 ?0.46 ns xc4vlx60 1.25 ?0.43 1.47 ?0.40 1.55 ?0.36 ns xc4vlx80 1.22 ?0.26 1.42 ?0.21 1.49 ?0.15 ns xc4vlx100 1.27 ?0.20 1.48 ?0.14 1.56 ?0.08 ns xc4vlx160 1.54 ?0.20 1.79 ?0.13 1.89 ?0.05 ns xc4vlx200 n/a 1.90 0.03 2.00 0.15 ns xc4vsx25 1.25 ?0.50 1.47 ?0.48 1.55 ?0.48 ns xc4vsx35 1.21 ?0.41 1.43 ?0.38 1.50 ?0.34 ns xc4vsx55 1.25 ?0.23 1.47 ?0.18 1.55 ?0.13 ns xc4vfx12 1.35 ?0.71 1.55 ?0.69 1.61 ?0.69 ns xc4vfx20 1.25 ?0.52 1.48 ?0.51 1.56 ?0.51 ns xc4vfx40 1.23 ?0.18 1.45 ?0.13 1.52 ?0.08 ns xc4vfx60 1.17 ?0.06 1.37 0.01 1.44 0.09 ns xc4vfx100 1.21 0.11 1.42 0.20 1.49 0.31 ns xc4vfx140 n/a 1.68 0.21 1.76 0.31 ns notes: 1. setup time is measured relative to the global clock input signal with the fastest r oute and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 2. these measurements include: clk0 dcm jitter iff = input flip-flop or latch 3. use ibis to determine any duty-cycle di stortion incurred using various standards. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 47 ta bl e 5 7 : global clock setup and hold for lvcmos25 st andard, with dcm in source-synchronous mode symbol description device speed grade units ? 12 ? 11 ? 10 example data input setup and hold times relative to a forwarded clock input pin, (1) using dcm and global clock buffer. for situations where clock and data inputs conform to different st andards, adjust the setup and hold values accordingly using the v alues shown in iob switching characteristics (1,2) , page 19 . t psdcm_0 / t phdcm_0 no delay global clock and iff (2) with dcm in source-synchronous mode xc4vlx15 ?0.33 0.73 ?0.33 0.88 ?0.33 1.03 ns xc4vlx25 ?0.29 0.86 ?0.29 0.97 ?0.29 1.09 ns xc4vlx40 ?0.37 0.90 ?0.37 1.04 ?0.37 1.19 ns xc4vlx60 ?0.32 1.02 ?0.32 1.15 ?0.32 1.29 ns xc4vlx80 ?0.38 1.18 ?0.38 1.34 ?0.38 1.50 ns xc4vlx100 ?0.31 1.24 ?0.31 1.41 ?0.31 1.57 ns xc4vlx160 ?0.31 1.50 ?0.31 1.69 ?0.31 1.89 ns xc4vlx200 n/a ?0.31 1.97 ?0.31 2.19 ns xc4vsx25 ?0.32 0.95 ?0.32 1.07 ?0.32 1.17 ns xc4vsx35 ?0.37 1.04 ?0.37 1.17 ?0.37 1.31 ns xc4vsx55 ?0.32 1.22 ?0.32 1.36 ?0.32 1.52 ns xc4vfx12 ?0.26 0.73 ?0.26 0.86 ?0.26 0.96 ns xc4vfx20 ?0.31 0.92 ?0.31 1.03 ?0.31 1.14 ns xc4vfx40 ?0.35 1.26 ?0.35 1.41 ?0.35 156 ns xc4vfx60 ?0.43 1.39 ?0.43 1.56 ?0.43 1.74 ns xc4vfx100 ?0.38 1.55 ?0.38 1.75 ?0.38 1.96 ns xc4vfx140 n/a ?0.44 2.03 ?0.44 2.25 ns notes: 1. the timing values were measured using t he fine-phase adjustment feature of the dcm. these measurements include clk0 dcm jitte r. package skew is not included in these measurements. 2. iff = input flip-flop virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 48 ta bl e 5 8 : global clock setup and hold for lvcmos25 standard, without dcm symbol description device speed grade units -12 -11 -10 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd /t phfd full delay global clock and iff (2) without dcm xc4vlx15 1.82 0.11 2.33 0.19 2.74 0.39 ns xc4vlx25 1.79 0.20 2.30 0.29 2.70 0.50 ns xc4vlx40 2.06 0.13 2.61 0.22 3.06 0.44 ns xc4vlx60 2.39 0.04 2.99 0.12 3.50 0.34 ns xc4vlx80 2.36 0.16 2.96 0.26 3.47 0.49 ns xc4vlx100 4.85 ?0.09 5.83 ?0.09 6.76 ?0.01 ns xc4vlx160 2.56 0.46 3.21 0.59 3.76 0.88 ns xc4vlx200 n/a 3.57 0.64 4.17 0.95 ns xc4vsx25 2.12 0.14 2.68 0.23 3.14 0.44 ns xc4vsx35 2.10 0.21 2.66 0.30 3.12 0.52 ns xc4vsx55 1.99 0.57 2.53 0.71 2.97 0.98 ns xc4vfx12 1.82 0.12 2.33 0.20 2.73 0.39 ns xc4vfx20 1.75 0.38 2.26 0.49 2.65 0.73 ns xc4vfx40 1.82 0.64 2.34 0.78 2.75 1.05 ns xc4vfx60 2.42 0.25 3.03 0.35 3.54 0.59 ns xc4vfx100 1.99 1.11 2.21 1.31 2.60 1.64 ns xc4vfx140 n/a 2.80 1.26 3.28 1.61 ns notes: 1. setup time is measured relative to the global clock input signal with the fastest r oute and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 2. iff = input flip-flop or latch. 3. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 49 chipsync? source-synchronous switching characteristics the parameters in this section provide the necessary values for calculating timing budgets for virtex-4 fpga source-synchronous transmitter and receiver data-valid windows. ta bl e 5 9 : duty cycle distortion and clock-tree skew symbol description device speed grade units -12 -11 -10 t dcd_clk global clock tree duty cycle distortion (1) all 150 150 150 ps t ckskew global clock tree skew (2) xc4vlx15 50 60 60 ps xc4vlx25 90 100 110 ps xc4vlx40 140 160 180 ps xc4vlx60 140 160 180 ps xc4vlx80 200 230 260 ps xc4vlx100 270 310 350 ps xc4vlx160 270 310 350 ps xc4vlx200 n/a 310 350 ps xc4vsx25 50 60 70 ps xc4vsx35 90 100 120 ps xc4vsx55 140 170 190 ps xc4vfx12 50 60 70 ps xc4vfx20 60 70 70 ps xc4vfx40 90 110 120 ps xc4vfx60 140 170 190 ps xc4vfx100 200 230 260 ps xc4vfx140 n/a 310 350 ps t dcd_bufio i/o clock tree duty cycle distortion all 100 100 100 ps i/o clock tree skew across one clock region all 50 50 50 ps t bufioskew i/o clock tree skew across multiple clock regions all 50 50 50 ps t dcd_bufr regional clock tree duty cycle distortion all 250 250 250 ps t bufio_max_freq i/o clock tree max frequency all 710 710 645 mhz t bufr_max_freq regional clock tree max frequency all 300 250 250 mhz notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be us ed to calculate any additional duty cycle distortion that might be caused by asymme trical rise/fall times. 2. the t ckskew value represents the worst-case vertical clock-tree skew observable between sequentia l i/o elements. signifi cantly less clock- tree skew exists for i/o registers that are close to each other and f ed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 50 ta bl e 6 0 : package skew symbol description device package value units t pkgskew package skew (1) xc4vlx15 sf363 80 ps ff668 120 ps xc4vlx25 sf363 90 ps ff668 110 ps xc4vlx40 ff668 110 ps ff1148 150 ps xc4vlx60 ff668 130 ps ff1148 140 ps xc4vlx80 ff1148 155 ps xc4vlx100 ff1148 140 ps ff1513 180 ps xc4vlx160 ff1148 145 ps ff1513 180 ps xc4vlx200 ff1513 180 ps xc4vsx25 ff668 90 ps xc4vsx35 ff668 100 ps xc4vsx55 ff1148 145 ps xc4vfx12 sf363 90 ps ff668 100 ps xc4vfx20 ff672 110 ps xc4vfx40 ff672 120 ps ff1152 150 ps xc4vfx60 ff672 110 ps ff1152 170 ps xc4vfx100 ff1152 150 ps ff1517 170 ps xc4vfx140 ff1517 150 ps notes: 1. these values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from pad to ball (7.1 ps per mm). 2. package trace length information is available for these device /package combinations. this information can be used to deskew t he package. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 51 production stepping the virtex-4 fpga stepping identification system denotes the capability improvement of production released devices. by definition, devices from one stepping are functional supersets of previous device s. bitstreams compiled for a device with an earlier stepping are guaranteed to operate correctly in subsequent device steppings. new device steppings can be shipped in place of earlier device steppings. existing production designs are guaran- teed on new device steppings. to take advantage of the capabilities of a newer device stepping, customers are able to order a new stepping version and compile a new bit- stream. production devices are marked with a stepping version, with the exception of some step 1 devices. designs should be compiled with a config stepping parameter set to a specific stepping version. th is parameter is set in the ucf file: config stepping = ?#?; (where # is the stepping version) the default stepping level used by the ise software is reported in the par report. ta bl e 6 3 shows the jtag id code by step. ta bl e 6 1 : sample window symbol description device speed grade units -12 -11 -10 t samp sampling error at receiver pins (1) all 450 500 550 ps t samp_bufio sampling error at receiver pins using bufio (2) all 350 400 450 ps notes: 1. this parameter indicates the total sampling error of virtex-4 fp ga ddr input registers across voltage, temperature, and proces s. the characterization methodology uses the dcm to capture the ddr i nput registers? edges of operati on. these measurements include: - clk0 dcm jitter - dcm accuracy (phase offset) - dcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-4 fp ga ddr input registers across voltage, temperature, and proces s. the characterization methodology uses the bufio clock network and idel ay to capture the ddr input registers? edges of operation. th ese measurements do not include package or clock tree skew. ta bl e 6 2 : chipsync pin-to-pin setup/hold and clock-to-out symbol description speed grade units -12 -11 -10 data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock across multiple clock regions ?0.45 0.97 ?0.45 1.08 ?0.44 1.17 ns pin-to-pin clock-to -out using bufio t ickofcs clock-to-out of i/o clock across multiple clock regions 4.10 4.54 5.02 ns table 63: jtag id code by step device step 0 step 1 step 2 xc4vlx15 35 xc4vlx25 9a xc4vlx40 35 xc4vlx60 2 or 3 4 or 5 xc4vlx80 35 xc4vlx100 2 or 3 4 or 5 xc4vlx160 0 or 3 4 or 5 xc4vlx200 0 or 3 2 or 5 xc4vsx25 24 xc4vsx35 24 xc4vsx55 24 xc4vfx12 0 or 2 xc4vfx20 26 xc4vfx40 0 xc4vfx60 28 xc4vfx100 06 xc4vfx140 04 notes: 1. shaded cells represent device s not produced at that stepping. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 52 current virtex-4 production devices ta bl e 6 4 summarizes the current production lx and sx device stepping. ta bl e 6 5 summarizes the current production fx device stepping. ta bl e 6 4 : current lx and sx production devices lx/sx device stepping step 1 step 2 example ordering code xc4vlx60-10ff672c xc4vlx60-10ff672cs2 device steppings shipped when ordered per example ordering code step 1 or step 2 step 2 capability improvements (1) ? the dfs macro is no longer needed ? t config requirement is removed ? dcm_reset requirement is removed ? dcm_input_clock_stop requirement is removed by a macro (automatically inserted by ise software) config stepping parameter (must be set in ucf file) ?1? ?2? minimum software required ise 7.1i sp4 ise 7.1i sp4 minimum speed specification required. 1.58 1.58 notes: 1. see lx and sx errata for details on lx and sx step 1 and es silicon. ta bl e 6 5 : current fx production devices fx device stepping step 0 step 1 example ordering code xc4vfx60-10ff1152c xc4vfx60-10ff1152cs1 device steppings shipped when ordered per example ordering code step 0 or step 1 step 1 capability improvements see fx errata for details config stepping parameter (must be set in ucf file) ?0? ?0? or ?1? minimum software required ise 8.1i sp2 ise 8.1i sp2 minimum speed specification required 1.58 1.58 notes: 1. speed specification v1.65 or later must be used for xc4vfx40 devices (all speed grades) and for xc4vfx100 (-12 speed grade on ly). in this case, these family members (and speed gr ades) are released to production before a speed sp ecification is released with the correct la bel (advance, preliminary, or production). these labeling discrepancies will be corrected in a subsequent speed s pecification release. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 53 revision history the following table shows the revision history for this document. date version revisions 08/02/04 1.0 initial xilinx releas e. printed handbook version. 09/09/04 1.1 edits in tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. removed table 39. 01/18/05 1.2 added parameters to tables 4 and 5. removed system monitor and adc parameters. 02/01/05 1.3 changed parameters in tables 1, 2, 3, 7, and 11. added interface performance characteristics section. added switching characteristics section and ta bl e 1 4 . added parameters to the following tables: 4?6, 14, 16?30, 32?40, and 46. 02/24/05 1.4 changed the notes in ta b l e 2 . added set/reset parameters to ta bl e 3 2 and ta bl e 3 3 . changed description in ta b l e 3 5 . changed set/reset in ta bl e 3 7 . changed psclk units in ta bl e 4 5 . added parameters to ta bl e 4 6 . changed dcm_tap_ms_min in ta bl e 5 0 . 05/19/05 1.5 added rocketio and powerpc parameters to ta bl e 1 , ta bl e 2 , and ta bl e 3 . removed conditions from v idiff and v icm in ta b l e 9 . revised ta bl e 1 3 . added rocketio dc input and output levels section. added powerpc switching characteristics section. added rocketio switching characteristics section. removed table 31 from version 1.4. revised ta bl e 3 5 . along with changes to ta bl e 4 3 and ta b l e 5 0 , there are three new requirements to ensure maximum operating frequencies for the dcm. added parameters to ta bl e 5 4 , ta bl e 5 5 , ta b l e 5 6 , ta bl e 5 8 , ta b l e 5 9 , ta b l e 6 0 , ta b l e 6 1 , ta b l e 6 2 . 06/17/05 1.6 revised v in and v ts in ta bl e 1 and note 4. revised typical p cpu specification in ta bl e 3 . revised symbols and values in the processor tables: ta bl e 1 6 through ta b l e 2 2 . revised t dcref in ta bl e 2 4 . corrected the clkout_freq_fx_hf_ms_min in ta bl e 4 5 , the clkout_freq_fx_lf_mr_min in ta b l e 4 6 , and the ?input clock period jitter? in ta bl e 4 7 . corrected units in ta b l e 5 9 . 06/27/05 1.7 changed v il and v ih for lvcmos15 in ta b l e 7 . revised ta bl e 1 4 . replaced value for v eye in ta b l e 2 5 . added note 4 to ta b l e 5 0 . added ta bl e 5 7 : global clock setup and hold for lvcmos25 standard, with dcm in source-synchronous mode . added value for xc4vlx160-ff1513 in ta b l e 6 0 . added values for -12 speed specifications to most of the tables. revised the -10 and -11 speeds in mo st of the switching characteristics tables. 08/06/05 1.8 updated to speed specification v1.56. added v cc_config note to ta b l e 2 . clarified design information in ta b l e 1 3 . corrected t program in ta bl e 4 3 . added drp configuration timing for dcms to ta bl e 4 3 . added global clock tree maximum frequency to ta b l e 4 4 . corrected clkout_freq_fx_lf_ms_min in ta b l e 4 5 . added footnotes 3 and 4 to ta b l e 4 5 and ta bl e 4 6 . added more data to the t ckskew in ta b l e 5 9 . 08/29/05 1.9 corrected v ocm in ta bl e 8 . revised ta bl e 1 1 . added rocketio mgt clock dc input levels to ta bl e 1 2 . revised sfi-4.1 performance values in ta b l e 1 3 . added software tools requirements ise7.1i sp4, to description above ta bl e 1 4 . added -11x speed grade to ta bl e 1 4 and ta b l e 2 3 . edited ta bl e 1 5 and ta bl e 1 6 . edited ta bl e 2 4 . added note 2 to ta bl e 2 5 , and moved rxoob vdpp to ta b l e 1 2 . added conditions to t dj and t rj in ta bl e 2 6 . moved txoob vdpp to ta bl e 1 2 . added rsds to ta b l e 2 7 . added note 4 to ta bl e 4 9 . added production stepping section. 09/28/05 1.10 ta bl e 2 : removed note 1. recommended maximum voltage drop for v ccaux is 10 mv/ms. virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 54 02/03/06 1.11 revised the speed specification requirements in switching characteristics , page 12 , with parameter changes in ta bl e 5 4 and ta bl e 5 6 . added note 7 to ta bl e 2 . added to the i rpu and i rpd specifications in ta b l e 3 . changed lvcmos18 to meet the jedec specification in ta bl e 7 . inserted notes into ta b l e 8 , ta b l e 9 , and ta bl e 1 0 . corrected note 1 in ta bl e 1 1 . in ta bl e 1 2 , revised common mode input voltage range (v icm ) typical from 800 mv to 600 mv and added a new note 1. also in ta b l e 1 2 , changed common mode voltage specification from 95mv to 950mv. changed performance numbers in ta b l e 2 3 . removed the typical specification for t dj from ta bl e 2 6 . added note 2 to ta bl e 2 7 . in ta b l e 3 5 , added maximum to t idelayctrlco_rdy , and a new parameter t idelaypat_jit . revised note 1 in ta bl e 4 3 . added note 5 to ta bl e 4 5 . revised notes 3 and 5 in ta b l e 5 0 . changed the clkin_freq_pmcd_clka_max -12 specification in ta bl e 5 3 . changed the t bufio_max_freq specification in ta b l e 5 9 . changed the information in the production stepping and current virtex-4 production devices sections. 03/22/06 1.12 modified second paragraph in power-on power supply requirements . added/changed numbers for i ccintmin , i ccauxmin , and i ccomin, and added note 2 ( ta b l e 5 ). changed the typ value of the dc parameter, common mode input voltage range from 600 mv to 800 mv in ta b l e 1 2 . added three dc parameters to ta bl e 1 2 , input common-mode voltage (v icmc ), peak-to-peak differential input voltage (v idiff ), and differential input resistance (r in ). changed the spi4.2 entry for -11 from 900 mb/s to 1 gb/s in ta b l e 1 3 . added note 3 to ta bl e 1 5 . reduced the maximum frequency from 322 mhz to 250 mhz (in ta bl e 2 5 and ta bl e 2 6 ). added note 5 to ta b l e 4 0 . 06/01/06 1.13 changed v in and v ts values and added notes to table 1, page 1 . removed -11x speed grade from ta bl e 1 4 . updated to speed specification v1.60. removed -11x speed grade, changed the -12 and -11 speed grade to 6.5 gb/s, and deleted note 1 in table 23, page 16 . deleted first condition and changed second condition to 2.5 gb/s to 6.5 gb/s for reference clock total jitter, peak-peak (t gjtt ) in table 24, page 16 . changed the max value for serial data rate f gtx to 6.5 gb/s. deleted first condition and changed second condition to 2.5 gb/s to 6.5 gb/s for serial data output deterministic jitter (t dj ) and deleted first condition and changed second condition to 2.5 gb/s to 6.5 gb/s for serial data output random jitter (t rj ), both in table 26, page 18 . 06/23/06 1.14.1 virtex-4 fpga electrical characteristics , page 1 : removed paragraph on that introduced the -11x for xc4vfx devices. table 3, page 3 : added new values for i ccauxrx , i ccauxtx , i cccauxmgt , i ttx , i trx , and new notes 2 and 3. table 4, page 4 : added new symbols and for values i ccauxrx , i ccauxtx , i ttx , i trx ,i aumgt and new notes 4 and 5. ta bl e 1 2 , page 11 : changed dc parameters and values and added note. ta bl e 1 4 : changed speed designations for the xc4vfx devices. table 24, page 16 and table 25, page 17, for most characteristics: changed conditions, speed grade (typ and max) values, and units. ta bl e 2 6 , page 18 , for most characteristics: changed conditions, speed grade (typ and max) values, and units. updated notes. table 43, page 36 : removed the tcnfig symbol, values, and note 1. note 2 is now note 1, and the reference has also been changed. table 50, page 42 : removed input signal requirements. table 54, page 44 , table 55, page 45 , ta b l e 5 6 , page 46 , table 57, page 47 , and table 58, page 48 : corrected large speed numbers to n/a. 08/23/06 1.15 table 24, page 16 : changed value for reference clock rise/fall time (t rclk ; t fclk ) from 65 ps typ to 400 ps max. table 35, page 29 : changed the speeds specification for the -12, -11, and -10 speed grades for t idelayresolution , deleted row for t idelayresolution_err and added row for t idelaytotal_err . table 39, page 32 : changed the speeds specification for -12 speed grades, sequential delay characteristics: t reg , t regxb , t regyb , t cksh , and t regf5 . table 65, page 52 : added stepping information for virtex-4 fx devices. date version revisions virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 55 09/07/06 1.16 added 2.5v rows to v in and v ts ( table 1, page 1 ). updated value dv in from 200 mv to 110 mv in table 12, page 11 . updated speed grade specificat ions for xcv4fx devices in ta bl e 1 4 . updated jitter tolerance and v eye in table 25, page 17 . corrected equation for t idelaytotal_err in table 35, page 29 . 10/06/06 1.17 ? speed specification version for this data sheet release: v1.62 . ? ta b l e 1 : removed former note 3 on v in . ? ta b l e 1 4 : moved xc4vfx12-11, xc4vfx20- 11, xc4vfx60-11, and xc4vfx100-11 devices to production status. ? ta b l e 1 5 : expanded to break out processo r clock specifications into characteristics when apu not used and characteristics when apu used . removed specs for cpmfcmclk, not available. ? ta b l e 2 5 , ta b l e 2 6 : updated rx and tx jitter data and notes. ? ta b l e 3 9 : modified t regxb , t regyb , and t cksh timing parameters to comply with v1.62 speed specification. 12/11/06 2.0 ? speed specification version for this data sheet release: v1.62 . ? ta b l e 1 : modified note (3) referring to 3.3v i/o design guidelines. added i in parameters. ? ta b l e 2 : corrected recommended v trx range to 0.25v ? 2.5v. added i in parameters. ? ta b l e 7 : added lvdci attributes with lvcmos. ? ta b l e 1 3 : added note (1) for sdr lvds interface requiring ac coupling above 622 mhz. added ddr2 sdram (high-performance serdes design) with reference to xapp721. updated all specification values. ? pin-to-pin performance and register-to-register performance tables (formerly table 13 and table 14) deleted. ? ta b l e 1 4 : xc4vfx12 changed to production status. ? ta b l e 1 5 : added apu-used max characteristics for -12 devices. ? ta b l e 2 4 : added values for spread-spectrum clocking and footnote. ? ta b l e 2 6 : changed symbol for jitter parameters from t j , r j , and d j to tj, rj, and dj respectively. ? ta b l e 3 2 : added note (1) to refer to timing report for non-zero tap values. made dly setup/hold parameters relative to c, not clkdiv. ? ta b l e 3 4 : amended note (1) to refer to timing report for non-zero tap values. ? ta b l e 3 5 : added note (1) to refer to xapp707 for details on idelay timing characteristics. changed t idelayresolution from 74 ps to 75 ps to match timing analyzer. modified formula for t idelaytotal_err to use 75 ps resolution. ? ta b l e 4 0 : added clk-to-dout parameters for ?with ecc? case. added clk-to-clk parameter. ? ta b l e 4 3 , ta b l e 4 4 , ta b l e 5 9 : added configuration parameter values for -12 speed grade. ? ta b l e 4 5 : added f max for -12 speed grade. ? ta b l e 4 5 , ta b l e 4 6 , ta b l e 4 7 : added note (6) stating that clkin values for dll only also apply to dll and dfs together. ? ta b l e 4 6 , ta b l e 4 7 : replicated note (5) from ta bl e 4 5 and applied to all clkin with dll parameters. ? ta b l e 4 7 , ta b l e 5 0 : added notes to clarify boundary-frequency cases. ? ta b l e 4 8 : modified note (1) to point to the architecture wizard for clkfx output jitter. added note (2) to indicate that pmcd outputs introduce no jitter. date version revisions virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 56 12/11/06 (cont?d) 2.0 (cont?d) ? ta b l e 5 0 : removed t_lock_fx_min pa rameter. added dcm_reset. ? ta b l e 5 3 : added note (1), no minimum frequency for pmcd. ? ta b l e 6 4 : added note (1) to refer to lx a nd sx errata for capability improvements. 03/27/07 2.1 ? speed specification version for this data sheet release: v1.64 . ? ta b l e 4 : added note (6) regarding max quiescent supply current. ? ta b l e 5 : filled in missing power-on cu rrent values for fx devices. ? ta b l e 2 4 : added new parameter f grefclk . added min value for spread spectrum clocking frequency. corrected ?conditions?. ? ta b l e 2 6 : revised notes (2) and (3). ? ta b l e 3 7 , ta b l e 3 8 : added column/values for xc4vfx -12. ? ta b l e 3 9 : added columns/values for xc4vfx -11 and -12. corrected xc4vlx/sx -11 and -12 values for t regxb , t regyb , and t cksh . ? ta b l e 4 3 : restored parameter t config and footnote (1) from earlier revision. added new parameter t smco (selectmap readback clock-to-out). ? ta b l e 5 0 : restored dcm_reset minimu m and dcm_input_clock_stop parameters from earlier revision. added notes (4) through (7) to these parameters. ? ta b l e 6 0 : removed ff1760 package. not supported. ? ta b l e 6 3 : added fx devices and jtag ids. 06/08/07 2.2 ? speed specification version for this data sheet release: v1.65 . ? ta b l e 1 4 : promoted -12 speed grade devices of xc4vfx12, xc4vfx20, and xc4vfx60 to production status. ? ta b l e 3 7 : removed parameter t iscck_rev . not meaningful because pin should always be connected to gnd. ? ta b l e 4 3 : added parameter f max_selectmap . for maximum slave selectmap mode external configuration clock frequency. ? ta b l e 6 3 : filled in step 1 values for xc4vfx20, xc4vfx60, and xc4vfx100. ? ta b l e 6 5 : added step 1 data. 08/10/07 2.3 ? speed specification version for this data sheet release: v1.65 . ? ta b l e 3 : added max value for i batt . ? ta b l e 2 5 : added unit (ns) to rxsigdet. ? ta b l e 2 7 : added note (3) specifying range of dci reference resistors and referring to ug070. ? added section ethernet mac switching characteristics , page 22 , and replaced ta b l e 2 9 . ? added section i/o standard adjustment measurement methodology , page 23 , including ta bl e 3 0 , ta bl e 3 1 , and figure 4 . ? ta b l e 4 3 : added parameter f max_icap . added word ?data? to description of selectmap setup/hold. ? ta b l e 6 4 : added to capability impr ovements, for step 1 that the dfs macro is no longer needed. 09/10/07 2.4 ? speed specification version for this data sheet release: v1.67 . ? ta b l e 1 4 : promoted all speed grades for xc4vfx40 devices, and -12 speed grade for xc4vfx100 devices, to production status. ? ta b l e 6 3 : filled in step 1 value for xc4vfx40. ? ta b l e 6 5 : added note 1. date version revisions virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 57 09/28/07 3.0 ? speed specification version for this data sheet release: v1.67 . ? promoted data sheet to production status. ? ta b l e 1 4 : moved xc4vfx140, all speed grades, from advance to production status. ? ta b l e 5 9 : added/updated all global clock tree skew values. qualified note (2) by adding ?vertical?. ? ta b l e 6 0 : added package skew values for xc 4vfx40, xc4vfx100, and xc4vfx140. ? ta b l e 6 3 : added jtag id code for xc4vfx140. 12/11/07 3.1 ? speed specification version for this data sheet release: v1.68 . ? added new copyright notice and legal disclaimer section. ? ta b l e 1 3 : removed table note references to xapp700, xapp704, and xapp705 (obsolete). renumbered table notes. ? ta b l e 1 5 : added new note 1, renumbered subsequent table notes. ? ta b l e 3 0 : removed table rows for lvpecl_33, lvds_33, and lvdsext_33. ? ta b l e 3 0 , ta b l e 3 1 : corrected ?electron-coupled? to ?emitter-coupled?. ? ta b l e 3 1 : for lvds extended mode 2.5v, corrected i/o standard attribute to lvdsext_25. ? ta b l e 3 7 : added note 4 specifying f tog for -11 fx devices as 1181 mhz. ? ta b l e 4 3 : added parameter f max_readback . ? ta b l e 5 8 : corrected t psfd for xc4vfx100 devices to 1.99 ns. ? section production stepping , page 51 : advised that current stepping level is reported by the ise tool in the par report. 04/10/08 3.2 ? speed specification version for this data sheet release: v1.68 . ? table 28, page 22 : re-inserted table. ? table 43, page 36 : updated symbol names for the drp entries. ? table 63, page 51 : revised code for xc4vfx40 package to 0. 06/06/08 3.3 ? speed specification version for this data sheet release: v1.68 . ? table 3, page 3 : in note (2), clarified differences between settings for typical and maximum i cc numbers. ? table 24, page 16 : revised f gclk to show different maximum frequencies depending on the speed grade. removed t phase . ? table 35, page 29 : reorganized according to idelayctrl and idelay. 11/26/08 3.4 ? table 35, page 29 : added f max . 06/16/09 3.5 ? table 40, page 33 : changed t rcko_doa to a max parameter. 08/13/09 3.6 ? table 3, page 3 : updated note 1. ? table 45, page 38 : added note 6 reference to and updated descriptions of clkin_freq_dll_hf_ms_min an d clkin_freq_fx_hf_ms_max. 09/09/09 3.7 ? table 7, page 8 : added ?lvcmos? to notes 3 and 4. date version revisions virtex-4 fpga data sheet: dc and switching characteristics ds302 (v3.7) september 9, 2009 www.xilinx.com product specification 58 notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. |
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